Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
3.1.24 Asynchronous System Trap Enable Register (ASTER)
The AST Interrupt Enable Register is a read/write register. It is used to enable
corresponding bits of the ASTRR requesting interrupts. There is a one-to-one correspondence
between the interrupt requests and enable bits, as with the reads of
the interrupt request IPRs, reads of the ASTER return the complete set of interrupt
enable registers, see the HIRR Table 9 for details.
Figure 20: ASTER
6
3
6
3
Write Format:
5
2
5
1
5
0
4
9
4
8
4
7
U S E K
IGN A A A A
IGN
E E E E
Read Format:
3
3
3
2
3
1
3
0
2
9
2
8
U S E K
S
P P
RAZ A A A A SIER[15..1] L HIER C C HIER
E E E E
E [2..0] 0 1 [5..3]
1
4
1
3
1
2
1
0
0
9
0
8
0
7
0
5
0
4
C
R
E
0
3
0
0
RAZ
0
0
ASTER
Functions Located on the DECchip 21064 35