Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
3.1.23 Software Interrupt Enable Register (SIER)
The Software Interrupt Enable Register is a read/write register. It is used to enable
corresponding bits of the SIRR requesting interrupts. There is a one-to-one correspondence
between the interrupt requests and enable bits, as with the reads of the
interrupt request IPRs, reads of the SIER return the complete set of interrupt enable
registers, see the HIRR Table 9 for details.
Figure 19: SIER
6
3
6
3
Write Format:
4
8
4
7
IGN SIER[15..1] IGN
Read Format:
3
3
3
2
3
1
3
0
2
9
2
8
3
3
U S E K
S
P P
RAZ A A A A SIER[15..1] L HIER C C HIER
E E E E
E [2..0] 0 1 [5..3]
34 Functions Located on the DECchip 21064
3
2
1
4
1
3
1
2
1
0
0
9
0
8
0
7
0
5
0
4
C
R
E
0
3
0
0
RAZ
0
0
SIER