Sable CPU Module Specification

3.1.22 Hardware Interrupt Enable Register (HIER)
Copyright © 1993 Digital Equipment Corporation.
The Hardware Interrupt Enable Register is a read/write register. It is used to enable
corresponding bits of the HIRR requesting interrupt. The PC0, PC1, SLE and CRE
bits of this register enable the performance counters, serial line and correctable read
interrupts. There is a one-to-one correspondence between the interrupt requests and
enable bits, as with the reads of the interrupt request IPRs, reads of the HIER return
the complete set of interrupt enable registers, see the HIRR Table 9 for details.
Figure 18: HIER
6
3
6
3
Write Format:
Read Format:
3
3
3
2
3
3
3
2
3
1
1
6
S
P
P
IGN L IGN C HIER[5..0] C IGN
E
1
0
3
1
3
0
2
9
2
8
1
4
U S E K
S
P P
C
RAZ A A A A SIER[15..1] L HIER C C HIER R RAZ
E E E E
E [2..0] 0 1 [5..3] E
1
3
1
2
1
5
1
4
1
0
0
9
0
8
0
7
0
9
0
8
0
5
0
7
0
4
0
3
0
2
C
R
E
0
0
0
0
HIER
Functions Located on the DECchip 21064 33