Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
3.1.21 Asynchronous Trap Request Register (ASTRR)
The Asynchronous Trap Request Register is a read/write register. It contains bits to
request AST interrupts in each of the processor modes. In order to generate an AST
interrupt, the corresponding enable bit in the ASTER must be set and the processor
must be in the selected processor mode or higher privilege as described by the current
value of the PS CM bits. In addition, AST interrupts are only enabled in the 21064 if
the SIER[2] is set. This provides a mechanism to lock out AST requests over certain
IPL levels. All interrupt requests are blocked while executing in PALmode. Reads of
the ASTRR return the complete set of interrupt request registers and summary bits,
see the HIRR Table 9 for details.
Figure 17: ASTRR
6
3
6
3
Write Format:
5
2
5
1
5
0
4
9
4
8
4
7
U S E K
IGN A A A A
IGN
R R R R
Read Format:
U S E K
RAZ ASTRR
[3..0]
32 Functions Located on the DECchip 21064
3
3
3
2
2
9
2
8
1
4
1
3
1
2
0
0
0
9
0
8
0
7
S
P P
SIRR L HIRR C C HIRR
[15..1] R [2..0] 0 1 [5..3]
0
5
0
4
C
R
R
0
3
A
T
R
0
2
S
W
R
0
1
H
W
R
0
0
0
0
R
A
Z
ASTRR