Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

3.1.16 Processor Status (PS) Copyright © 1993 Digital Equipment Corporation. The processor status register is a read/write register containing only the current mode bits of the architecturally defined PS. Figure 12: PS 6 3 6 3 Write Format: Read Format: C C IGN M M IGN 1 0 3 5 3 4 RAZ C M 1 RAZ 3 3 Functions Located on the DECchip 21064 25 0 5 0 4 0 3 0 2 0 2 0 1 C M 0 0 0 0 0 R A Z PS
Copyright © 1993 Digital Equipment Corporation. 3.1.17 Exception Summary Register (EXC_SUM) The exception summary register records the various types of arithmetic traps that have occurred since the last time the EXC_SUM was written (cleared). When the result of an arithmetic operation produces an arithmetic trap, the corresponding EXC_SUM bit is set. In addition, the register containing the result of that operation is recorded in the exception register write mask IPR, as a single bit in a 64-bit field specifying registers F31-F0 and I31-I0. This IPR is visible only through the EXC_SUM register. The EXC_SUM register provides a one-bit window to the exception register write mask. Each read to the EXC_SUM shifts one bit in order F31-F0 then I31-I0. The read also clears the corresponding bit. Therefore, the EXC_SUM must be read 64 times to extract the complete mask and clear the entire register. Any write to EXC_SUM clears bits [8..2] and does not affect the write mask. The write mask register bit clears three cycles after a read. Therefore, code intended to read the register must allow at least three cycles between reads to allow the clear and shift operation to complete in order to ensure reading successive bits. Figure 13: EXC_SUM 6 3 3 4 3 3 RAZ M S K RAZ 26 Functions Located on the DECchip 21064 3 2 9 8 7 6 5 4 3 2 1 0 I O V I N E U N F F O V D Z E I N V S W C R A Z EXC_SUM
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7 and 8: 7.1.1 Exception Handling ..........
Page 9 and 10: 11.4 Environmental Specifications -
Page 11 and 12: 25 MM_CSR .........................
Page 13 and 14: 27 Base Addresses for CSRs . . . ..
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
Page 41: Copyright © 1993 Digital Equipment
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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