Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

3.1.11 Serial Line Clear Register (SL_CLR) Copyright © 1993 Digital Equipment Corporation. This write-only register clears the serial line interrupt request, the performance counter interrupt request and the CRD interrupt request. Therefore, the write of any data to the SL_CLR register will clear the remaining serial line interrupt request. The 21064 requires that the indicated bit be written with a zero to clear the selected interrupt source. Figure 10: SL_CLR 6 3 Table 7: SL_CLR 3 3 Field Type Description 3 2 3 1 1 6 S P P IGN L IGN C IGN C IGN C 1 0 CRD W0C Clears the correctable read error interrupt request. PC1 W0C Clears the performance counter 1 interrupt request. PC0 W0C Clears the performance counter 0 interrupt request. SLC W0C Clears the serial line interrupt request. 3.1.12 Serial Line Receive Register (SL_RCV) 1 5 1 4 1 3 1 2 1 1 1 0 0 9 0 8 7 7 0 6 0 5 0 4 0 3 0 2 C R D 0 1 0 0 IGN SL_CLR The serial line receive register contains a single read-only bit used with the interrupt control registers and the sRomD_h and sRomClk_h pins to provide an on-chip serial line function. The RCV bit is functionally connected to the sRomD_h pin after the I-Cache is loaded from the external serial ROM. Reading the RCV bit can be used to receive external data one bit at a time under a software timing loop. A serial line interrupt is requested on detection of any transition on the receive line which sets the SL_REQ bit in the HIRR. Using a software timing loop, the RCV bit can be read to receive data one bit at a time. The serial line interrupt can be disabled by clearing the HIER register SL_ENA bit. (See figure Figure 11) Functions Located on the DECchip 21064 23
Copyright © 1993 Digital Equipment Corporation. Figure 11: SL_RCV 6 3 RAZ R C V RAZ 3.1.13 Instruction Translation Buffer Zap Register (ITBZAP) 0 4 0 3 0 2 0 0 SL_RCV A write of any value to this IPR invalidates all twelve ITB entries. It also resets the NLU pointer to its initial state. The ITBZAP register should only be written in PALmode. 3.1.14 Instruction Translation Buffer ASM Register (ITBASM) A write of any value to this IPR invalidates all ITB entries in which the ASM bit is equal to zero. The ITBASM register should only be written in PALmode. 3.1.15 Instruction Translation Buffer IS Register (ITBIS) A write of any value to this IPR invalidates all twelve ITB entries. It also resets both the NLU pointer to their initial state. The ITBIS register should only be written in PALmode. 24 Functions Located on the DECchip 21064
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7 and 8: 7.1.1 Exception Handling ..........
Page 9 and 10: 11.4 Environmental Specifications -
Page 11 and 12: 25 MM_CSR .........................
Page 13 and 14: 27 Base Addresses for CSRs . . . ..
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
Page 39: Copyright © 1993 Digital Equipment
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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