Sable CPU Module Specification

3.1.11 Serial Line Clear Register (SL_CLR)
Copyright © 1993 Digital Equipment Corporation.
This write-only register clears the serial line interrupt request, the performance
counter interrupt request and the CRD interrupt request. Therefore, the write of any
data to the SL_CLR register will clear the remaining serial line interrupt request.
The 21064 requires that the indicated bit be written with a zero to clear the selected
interrupt source.
Figure 10: SL_CLR
6
3
Table 7: SL_CLR
3
3
Field Type Description
3
2
3
1
1
6
S
P
P
IGN L IGN C IGN C IGN
C
1
0
CRD W0C Clears the correctable read error interrupt request.
PC1 W0C Clears the performance counter 1 interrupt request.
PC0 W0C Clears the performance counter 0 interrupt request.
SLC W0C Clears the serial line interrupt request.
3.1.12 Serial Line Receive Register (SL_RCV)
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
7
7
0
6
0
5
0
4
0
3
0
2
C
R
D
0
1
0
0
IGN
SL_CLR
The serial line receive register contains a single read-only bit used with the interrupt
control registers and the sRomD_h and sRomClk_h pins to provide an on-chip serial
line function. The RCV bit is functionally connected to the sRomD_h pin after the
I-Cache is loaded from the external serial ROM. Reading the RCV bit can be used to
receive external data one bit at a time under a software timing loop. A serial line
interrupt is requested on detection of any transition on the receive line which sets
the SL_REQ bit in the HIRR. Using a software timing loop, the RCV bit can be read
to receive data one bit at a time. The serial line interrupt can be disabled by clearing
the HIER register SL_ENA bit. (See figure Figure 11)
Functions Located on the DECchip 21064 23