Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Figure 5: TB_TAG_FIG 6 3 6 3 Small Page Format: 4 4 3 2 Copyright © 1993 Digital Equipment Corporation. 1 1 3 2 IGN VA[42..13] IGN GH = 11(bin) Format (DTB only): IGN 4 4 3 2 2 2 2 1 VA[42..22] IGN 0 0 0 0 TB_TAG Functions Located on the DECchip 21064 17
Copyright © 1993 Digital Equipment Corporation. 3.1.7 Instruction Translation Buffer Page Table Entry Register (ITB_PTE) The ITB PTE register is a read/write register representing the twelve ITB page table entries. The first eight provide small page (8K byte) translations while the remaining four provide large page (4M byte) translations. The entry to be written is chosen by a not-last-used algorithm implemented in hardware. Writes to the ITB_PTE use the memory format bit positions as described in the Alpha Architecture Handbook with the exception that some fields are ignored. To ensure the integrity of the ITB, the ITB’s tag array is updated simultaneously from the internal tag register when the ITB_PTE register is written. Reads of the ITB_ PTE require two instructions. First, a read from the ITB_PTE sends the PTE data to the ITB_PTE_TEMP register, then a second instruction reading from the ITB_PTE_ TEMP register returns the PTE entry to the register file. Reading or writing the ITB_PTE register increments the TB entry pointer corresponding to the large/small page selection indicated by the TB_CTL, which allows reading the entire set of ITB_ PTE register entries. Reading and writing the ITB_PTE register is only performed while in PALmode regardless of the state of the HWE bit in the ICCSR IPR. Figure 6: ITB_PTE 6 3 6 3 Write Format: 5 3 5 2 3 2 3 1 U S E K IGN PFN[33..13] IGN R R R R IGN E E E E Read Format: RAZ 18 Functions Located on the DECchip 21064 3 4 A S M 3 3 1 3 1 2 1 2 1 1 1 1 U S E K PFN[33..13] R R R R RAZ E E E E 1 0 1 0 0 9 0 9 0 8 0 8 0 7 0 7 0 6 0 6 0 5 0 5 0 4 A S M 0 4 0 3 0 3 0 2 0 1 IGN 0 2 0 1 0 0 0 0 ITB_PTE
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7 and 8: 7.1.1 Exception Handling ..........
Page 9 and 10: 11.4 Environmental Specifications -
Page 11 and 12: 25 MM_CSR .........................
Page 13 and 14: 27 Base Addresses for CSRs . . . ..
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
Page 33: Copyright © 1993 Digital Equipment
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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