Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
When the processor receives an interrupt request and that request is enabled, hardware
reports or delivers an interrupt to the exception logic if the processor is not
currently executing PALcode. Before vectoring to the interrupt service PAL dispatch
address, the pipeline is completely drained and all outstanding data cache fills are
completed. The restart address is saved in the Exception Address IPR (EXC_ADDR)
and the processor enters PALmode. The cause of the interrupt may be determined
by examining the state of the interrupt request registers.
NOTE
Hardware interrupt requests are level-sensitive and, therefore, may be removed
before an interrupt is serviced. If they are removed before the interrupt
request register is read, the register will return a zero value.
3.1.5 Performance Counters
The 21064 chip contains a performance recording feature. The implementation of
this feature provides a mechanism to count various hardware events and cause an
interrupt upon counter overflow. Interrupts are triggered six cycles after the event,
and therefore, the exception program counter may not reflect the exact instruction
causing counter overflow. Two counters are provided to allow accurate comparison
of two variables under a potentially non-repeatable experimental condition. Counter
inputs include:
• Issues
• Non-Issues
• Total cycles
• Pipe dry
• Pipe freeze
• Mispredicts and cache misses
• Counts for various instruction classifications
In addition, the 21064 provides one chip pin input to each counter to measure external
events at a rate determined by the selected system clock speed.
They are reset to zero on power-up, but are otherwise never cleared. They are intended
as a means of counting events over a long period of time relative to the event
frequency and therefore provide no means of extracting intermediate counter values.
Because the counters continuously accumulate selected events despite interrupts being
enabled, the first interrupt after selecting a new counter input has an error bound
as large as the selected overflow range.
In addition, some inputs may over count events occurring simultaneously with Dstream
errors which abort the actual event very late in the pipeline. For example,
when counting load instructions, attempts to execute a load resulting in a DTB miss
exception will increment the performance counter after the first aborted execution
attempt and again after the TB fill routine when the load instruction reissues and
completes.
14 Functions Located on the DECchip 21064