Sable CPU Module Specification

3.1.4 Interrupt Logic
Copyright © 1993 Digital Equipment Corporation.
The 21064 chip supports three sources of interrupts.
• Hardware
There are six level-sensitive hardware interrupts sourced by pins.
• Software
There are fifteen software interrupts sourced by an on-chip IPR (SIRR).
• Asynchronous system trap (AST)
There are four AST interrupts sourced by a second internal IPR (ASTRR).
All interrupts are independently maskable by on-chip enable registers to support a
software controlled mechanism for prioritization. In addition, AST interrupts are
qualified by the current processor mode and the current state of SIER [2].
By providing distinct enable bits for each independent interrupt source, a software
controlled interrupt priority scheme can be implemented by PALcode or the operating
system with maximum flexibility.
For example, the 21064 can support a six-level interrupt priority scheme through
the six hardware interrupt request pins. This is done by defining a distinct state
of the hardware interrupt enable register (HIER) for each interrupt priority level
(IPL). The state of the HIER determines the current interrupt priority. The lowest
interrupt priority level is produced by enabling all six interrupts, for example bits
. The next is produced by enabling bits and so on, to the highest interrupt
priority level that is produced by enabling only bit 6 , and disabling bits . When
all interrupt enable bits are cleared, the processor can not be interrupted from the
hardware interrupt request register (HIRR). Each state, (, , , ,
, ) represents an individual IPL. If these states are the only states allowed
in the HIER, a six-level hardware interrupt priority scheme can be controlled entirely
by PAL software.
The scheme is extensible to provide multiple interrupt sources at the same interrupt
priority level by grouping enable bits. Groups of enable bits must be set and cleared
together to support multiple interrupts of equal priority level. This method reduces
the total available number of distinct levels.
Because enable bits are provided for all hardware, software, and AST interrupt requests,
a priority scheme can span all sources of processor interrupts. The only
exception to this rule is the following restriction on AST interrupt requests:
Four AST interrupts are provided, one for each processor mode. AST interrupt
requests are qualified such that AST requests corresponding to a given mode are
blocked whenever the processor is in a higher mode regardless of the state of
the AST interrupt enable register. In addition, all AST interrupt requests are
qualified in the 21064 with SIER[2].
Functions Located on the DECchip 21064 13