Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
• A bus interface unit, that contains logic that directly controls one bank of external
cache RAMs, and processes ‘‘easy’’ cycles without any CPU module action.
• A serial ROM interface for booting and diagnostics for chip and module level test
support
• A clock generator.
The 21064 CPU chip consists of three independent execution units: integer execution
unit (E-box), floating point unit (F-box), and the address generation, memory
management, write buffer and bus interface unit (A-box). Each unit can accept at
most one instruction per cycle, however if code is properly scheduled, this CPU chip
can issue two instructions to two independent units in a single cycle. A fourth box,
the (I-box), is the central control unit. It issues instructions, maintains the pipeline,
and performs all of the PC calculations.
3.1.1 I-box Internal Processor Registers
The primary function of the I-box is to issue instructions to the E-box, A-box, and
F-box. The I-box decodes two instructions in parallel and checks that the required
resources are available for both instructions. Section 3.1.6 through Section 3.1.25
describe the I-box internal processor registers. In order to provide those instructions,
the Ibox contains:
• The prefetcher
• PC pipeline
• ITB
• Abort logic
• Register conflict or dirty logic
• Exception logic
The Ibox decodes two instructions in parallel and checks that the required resources
are available for both instructions.
If resources are available then both instructions are issued. See Section 3.8.5 for
details on instructions that can be dual issued.The Ibox does not issue instructions
out of order; if the resources are available for the second instruction, but not for the
first instruction, then the Ibox issues neither. The resources for the first instruction
must be available before the Ibox issues any instructions. If the Ibox issues only
the first of a pair of instructions, the Ibox does not advance another instruction to
attempt dual issue again. Dual issue is only attempted on aligned quadword pairs.
3.1.2 Branch Prediction Logic
The Ibox contains the branch prediction logic. The 21064 offers a choice of branch prediction
strategies selectable through the ICCSR IPR. The Icache records the outcome
of branch instructions in a single history bit provided for each instruction location in
the Icache. This information can be used as the prediction for the next execution of
Functions Located on the DECchip 21064 11