Sable CPU Module Specification

CHAPTER 3
FUNCTIONS LOCATED ON THE DECCHIP 21064
3.1 21064 Chip Features
The DECchip 21064 microprocessor is the first in a family of chips to implement the
Alpha AXP architecture. The DECchip 21064 is a .75 micron CMOS (.5 micron for
the DECchip 21064-A275) based super-scalar super-pipelined processor using dual
instruction issue. The 21064 chip is packaged in a 431-pin (24x24, 100-mil pin pitch)
PGA package.
The 21064 and associated PALcode implement IEEE single and double precision,
VAX F_floating and G_floating datatypes and supports longword (32-bit) and quadword
(64-bit) integers. Byte (8-bit) and word (16-bit) support is provided by byte
manipulation instructions. Limited hardware support is provided for the VAX D_
floating datatype.
(G_floating and S_floating)
The architecturally optional instructions RCC is also implemented.
Other 21064 features include:
• Peak instruction execution of 380 million operations per second at a 190-MHz
clock rate (275 MHZ for DECchip 21064-A275)
• Flexible external interface supporting a complete range of system sizes and performance
levels while maintaining peak CPU execution speed
• Selectable data bus width and speed: 64-bit or 128-bit width, 75 MHz to 18.75
MHz bus speed
• An internal clock generator providing a high-speed chip clock and a pair of programmable
system clocks (CPU/2 to CPU/8)
• Support for external secondary cache including programmable cache size and
speed
• An on-chip write buffer with four 32-byte entries, with ‘‘byte merging’’ capability.
• An on-chip pipelined floating point unit capable of executing both DEC and IEEE
floating point instructions. The floating point unit can accept a new instruction
every cycle, except for divide instructions. The operate-to-operate latency for all
instructions other than divide is six CPU cycles. The latencies for single and
double precision divide instructions are shown in Table 2.
Functions Located on the DECchip 21064 9