Sable CPU Module Specification

INDEX
21064
IEEE floating point conformance, 57
PALcode instructions, 70
A
Aborts, 61
Abox, 37
data translation buffer, 53
load silos, 54
write buffer, 55
Abox IPRs, 37
ABOX_CTL, 42
Algorithms
Update vs Invalidate, 104
Alpha AXP
PALcode instructions, 69
ALT_MODE, 46
ASTER, 35
ASTRR, 32
B
Back-up Cache (B-Cache), 83
Back-up Cache Cycle Time, 101
BARRIER cycle, 143
BARRIER transaction, 153
B-Cache
see Back-up Cache
behavior on tag control parity error, 170
behavior on tag parity error, 169
defined, vi
B-Cache Control Register - CSR0, 86
B-Cache Control Register Definitions, 85
B-Cache Correctable Error Address Register -
CSR2, 95
B-Cache Correctable Error Register - CSR1,
92
B-Cache Initialization, 189
B-Cache Uncorrectable Error Address Register
- CSR4, 100
B-Cache Uncorrectable Error Register - CSR3,
97
BC_TAG, 79
BIU, vi
BIU_ADDR, 75
BIU_STAT, 74
Block diagrams
C4 chip, 3
CPU chip, 4
CPU module, 1
Branch prediction logic, 11
Bus interface unit, 54
BYSTANDER
defined, vi
C
C 3 Revision Register - CSR15, 128
C4
defined, vi
C4block diagram, 3
C4 subsystems, 3
Cache
cycle time, 102
invalidate management, 165
System-bus B-Cache Access Time, 102
CACHE BLOCK
defined, vi
Cache Block Merge Buffer, 102
Cache Block Prefetch
lack of, 107
Cache hit
defined, vi
CACHE LINE
defined, vi
Cache miss
defined, vii
Cache organization, 59
CC, 46
CC_CTL, 46
CLEAN
defined, vi
Cobra-bus
defined, vi
COMMAND
defined, vi
Index–1