Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. • BC_TAG holds results of external cache tag probe if external cache was enabled for this transaction C.8.1.2 BIU: tag address parity error • recognized at end of tag probe sequence • lookup uses predicted parity so transaction misses the external cache • BC_TAG holds results of external cache tag probe • machine check if enabled by ABOX_CTL[MCHK_EN] • BIU_STAT: BC_TPERR set • BIU_ADDR holds address C.8.1.3 BIU: tag control parity error • recognized at end of tag probe sequence • transaction forced to miss external cache • BC_TAG holds results of external cache tag probe • machine check if enabled by ABOX_CTL[MCHK_EN] • BIU_STAT: BC_TCPERR set • BIU_ADDR holds address C.8.1.4 BIU: system transaction terminated with CACK_HERR • machine check if enabled by ABOX_CTL[MCHK_EN] • BIU_STAT: BIU_HERR set, BIU_CMD holds cReq_h[2..0] • BIU_ADDR holds address C.8.2 Response to Multiple Errors This section describes the 21064’s response to multiple hardware errors, that is, to errors which occur after an initial error and before execution of the PALcode exception handler associated with that initial error. The 21064 error reporting hardware consists of two sets of independent error reporting registers. • BIU_STAT[7..0] and BIU_ADDR contain information about the following hardware errors: • Correctable or uncorrectable errors reported with CAck_h[2..0] by system components • Tag probe parity errors in the tag address or tag control fields • BIU_STAT[14..8], FILL_ADDR and FILL_SYNDROME contain error information about data fill errors. Cobra Specific ( Privileged Architecture Library Code ) PALcode 241
Copyright © 1993 Digital Equipment Corporation. The BC_TAG register contains information which can relate to any of the error conditions listed above. Each of the above two sets of error registers can contain information about either corrected or uncorrected hardware errors. When a hardware error occurs information about that error is loaded into the appropriate set of error registers and those registers are locked against further updates until PALcode explicitly unlocks them. If a second error occurs between the time that an initial error occurs and the time that software unlocks the associated error reporting registers, information about the second is lost. When the 21064 recognizes the second error it still posts the required corrected read interrupt or machine check, however it does not overwrite information previously locked in an error reporting register. If the second hardware error is not correctable and the error reporting register normally associated with this second error is already locked, the 21064 will set a bit to indicate that information about an uncorrecable hardware error was lost. Each set of error reporitng registers has a bit to report these fatal errors. For example, BIU_STAT[FATAL1] is set by hardware to indicate that a tag probe parity error or HARD_ERROR terminated external transaction occurred while BIU_ STAT[6..0], BIU_ADDR and BC_TAG were already locked due to some previous error. Similarly, BIU_STAT[FATAL2] is set by hardware to indicate that a primary cache fill received either a parity or single or dobule bit EDC error while BIU_STAT[13..8], FILL_ADDR, FILL_SYNDROME, and BC_TAG were already locked. 242 Cobra Specific ( Privileged Architecture Library Code ) PALcode
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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Page 203 and 204: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
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Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
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Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
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Page 257 and 258: INDEX 21064 IEEE floating point con
Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261: STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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