Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. 4. The first cycle (the first one or two instructions) at all PALcode entry points may not execute a conditional branch or any other instruction that uses the jsr stack hardware. This includes instructions JSR, JMP, RET, COROUTINE,BSR,HW_ REI and all Bxx opcodes except BR, which is allowed. 5. The following table indicates the number of cycles required after a HW_MTPR instruction before a subsequent HW_REI instruction for the specified IPRs. These cycles can be insured by inserting one HW_MFPR R31,0 instruction or other appropriate instruction(s) for each cycle of delay required after the HW_MTPR. IPR Cycles between HW_MTPR and HW_REI xTBIS,ASM,ZAP 0 xIER 2 xIRR 2 ICCSR[FPE] 3 ICCSR[ASN] 5 FLUSH_IC[ASM] 6 C.6 Powerup The table below lists the state of all the IPRs immediately following reset. The table also specifies which IPRs need to be initialized by power-up PALcode. Table 92: IPR Reset State IPR Reset State Comments ITB_TAG undefined ITB_PTE undefined ICCSR cleared except Floating point disabled, single issue mode, VAX mode ASN, PC0, PC1 enabled, ASN = 0, jsr predictions disabled, branch predictions disabled, branch history table disabled, performance counters reset to zero, Perf Cnt0(16b) : Total Issues/2, Perf Cnt1(12b) : Dcache Misses ITB_PTE_TEMP undefined EXC_ADDR undefined SL_RCV undefined ITBZAP n/a PALcode must do a itbzap on reset. ITBASM n/a ITBIS n/a PS undefined PALcode must set processor status. EXC_SUM undefined PALcode must clear exception summary and exception register write mask by doing 64 reads. PAL_BASE cleared Cleared on reset. Cobra Specific ( Privileged Architecture Library Code ) PALcode 235
Copyright © 1993 Digital Equipment Corporation. Table 92 (Cont.): IPR Reset State IPR Reset State Comments HIRR n/a SIRR undefined PALcode must initialize. ASTRR undefined PALcode must initialize. HIER undefined PALcode must initialize. SIER undefined PALcode must initialize. ASTER undefined PALcode must initialize. SL_XMIT undefined PALcode must initialize. Appears on external pin. DTB_CTL undefined PALcode must select between SP/LP dtb prior to any TB fill. DTB_PTE undefined DTB_PTE_TEMP undefined MMCSR undefined Unlocked on reset. VA undefined Unlocked on reset. DTBZAP n/a PALcode must do a dtbzap on reset. DTBASM n/a DTBIS n/a BIU_ADDR undefined Potentially locked. BIU_STAT undefined Potentially locked. SL_CLR undefined PALcode must initialize. DC_ADDR undefined Potentially locked. DC_STAT undefined Potentially locked. FILL_ADDR undefined Potentially locked. ABOX_CTL see comments [11..0]
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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Page 197 and 198: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
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Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
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Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
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Page 257 and 258: INDEX 21064 IEEE floating point con
Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261: STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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