Sable CPU Module Specification

HW_MTPR Rx,ITBIS
HW_MTPR Ry,DTBIS
Copyright © 1993 Digital Equipment Corporation.
5. An MXPR ITB_TAG, ITB_PTE, ITB_PTE_TEMP cannot follow a HW_REI that
remains in PAL mode. (Address bit of the EXC_ADDR is set) This rule implies
that it is not a good idea to ever allow exceptions while updating the ITB. If an
exception interrupts flow of the ITB miss routine and attempts to REI back, and
the return address begins with a HW_MxPR instruction to an ITB register, and
the REI is predicted correctly to avoid any delay between the two instructions,
then the ITB register will not be written. Code example:
HW_REI ; return from interrupt
HW_MTPR R1,ITB_TAG ; attempts to execute very next cycle, instr ignored
6. The ITB_TAG,ITB_PTE and ITB_PTE_TEMP registers can only be accessed in
PAL mode. If the instructions HW_MTPR or HW_MFPR to/from the above registers
are attempted while not in PAL mode by setting the HWE (hardware enable)
bit of the ICCSR, the instructions will be ignored.
7. Machine check exceptions taken while in PAL mode may load the EXC_ADDR
register with a restart address one instruction earlier than the proper restart
address. Some HW_MxPR instructions may have already completed execution
even though the restart address indicates the HW_MxPR as the return instruction.
Re-execution of some HW_MxPR instructions can alter machine state. (e.g.
TB pointers, EXC_ADDR register mask)
The mechanism used to stop instruction flow during machine check exceptions
causes the machine check exception to appear as a D-stream fault on the following
instruction in the hardware pipeline. In the event that the following instruction
is a HW_MxPR, a D-stream fault will not abort execution in all cases. Although
the EXC_ADDR will be loaded with the address of the HW_MxPR instruction as
if it were aborted, a HW_REI to this restart address will incorrectly re-execute
this instruction.
Machine check service routines should check for MXPR instructions at the return
address before continuing.
8. When writing the PAL_BASE register, exceptions may not occur. An exception
occurring simultaneously with a write to the PAL BASE may leave the register in
a metastable state. All asynchronous exceptions but reset can be avoided under
the following conditions:
PAL mode .................... blocks all interrupts
machine checks disabled ..... blocks I/O error exceptions
(via ABOX_CTL reg or MB isolation)
Not under trap shadow ....... avoids arithmetic traps
The trap shadow is defined as :
less than 3 cycles after a non-mul integer operate that may overflow
less than 22 cycles after a MULL/V instruction
less than 24 cycles after a MULQ/V instruction
less than 6 cycles after a non-div fp operation that may cause a trap
less than 34 cycles after a DIVF or DIVS that may cause a trap
less than 63 cycles after a DIVG or DIVT that may cause a trap
9. The sequence HW_MTPR PTE, MTPR TAG is NOT allowed. At least two null
cycles must occur between HW_MTPR PTE and HW_MTPR TAG.
Cobra Specific ( Privileged Architecture Library Code ) PALcode 233