Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Note that PALcode at PAL entry points of higher priority than DTBMISS must unlock possible MMCSR IPR and VA IPR locks. Table 90: PAL Entry Points Entry Name Time Offset(Hex) Cause RESET anytime 0000 MCHK pipe_stage[7] 0020 Uncorrected hardware error. ARITH anytime 0060 Arithmetic exception. INTERRUPT anytime 00E0 Includes corrected hardware error. D-stream errors pipe_stage[6] 01E0, 08E0, 09E0, 11E0 See Table 91. ITB_MISS pipe_stage[5] 03E0 ITB miss. ITB_ACV pipe_stage[5] 07E0 I-stream access violation. CALLPAL pipe_stage[5] 2000,40,80 thru 3FC0 128 locations based on instruction[7,5:0]. If bit[7] equals zero and CM does not equal kernel mode then an OPDEC exception occurs. OPCDEC pipe_stage[5] 13E0 Reserved or privileged opcode. FEN pipe_stage[5] 17E0 FP op attempted with : FP instructions disabled via ICCSR FPE bit FP IEEE round to +/- infinity FP IEEE with datatype field other than S,T,QW PALcode functions are implemented via the CALL_PAL instruction. CALL_PAL instructions cause exceptions in the hardware. As with all exceptions, the EXC_ADDR register is loaded by hardware with a possible return address. CALL_PAL exceptions do not load the EXC_ADDR register with the address of the CALL_PAL instruction. Rather, they load the EXC_ADDR register with the address of the instruction following the CALL_PAL. For this reason, the 21064 PALcode supporting the desired PAL mode functions need not increment the EXC_ADDR register before executing a HW_REI instruction to return to native mode. This feature requires special handling in the arithmetic trap and machine check PALcode flows for the 21064. To improve the speed of execution, a limited number of CALL_PAL instructions are directly supported in hardware with dispatches to specific address offsets. The 21064 provides the first 64 priviledged and 64 unpriviledged CALL_PAL instructions with larger code regions of 64 bytes. This produces hardware PAL entry points as described below. Priviledged CALL_PAL Instructions [00000000:0000003F] Offset(HEX) = 2000 + ([5:0] shift left 6) Unpriviledged CALL_PAL Instructions [00000080:000000BF] Offset(HEX) = 3000 + ([5:0] shift left 6) Cobra Specific ( Privileged Architecture Library Code ) PALcode 229
Copyright © 1993 Digital Equipment Corporation. The 21064 CALL_PAL instructions that do not fall within the ranges [00000000:0000003F] and [00000000:000000BF] result in an OPCDEC exception. In addition, CALL_PAL instructions that fall within the range [00000000:0000003F] while the 21064 is not executing in kernel mode will result in an OPCDEC exception. The PAL entry points assigned to D-stream errors require a bit more explanation. The hardware recognizes four classes of D-stream memory management errors: bad virtual address (improper sign extension), DTB miss, alignment error and everything else (ACV, FOR, FOW). These errors get mapped into four PAL entry points: UN- ALIGN, DTB_MISS PAL mode, DTB_MISS Native mode and D_FAULT. Table 90 lists the priority of these entry points as a group with respect to each of the other entry points. Since a particular D-stream memory reference may generate errors which fall into more than one of the four error classes which the hardware recognizes, we also must define the priority of each of the D-stream PAL entry points with respect to the others in the D-stream PAL entry group. Table 91 gives this priority. The PAL entry point 8E0 for Native mode DTB_MISS is only available in the 21064. EV3 provides only one DTB_MISS PAL entry point at address offset 9E0. 230 Cobra Specific ( Privileged Architecture Library Code ) PALcode
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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Page 191 and 192: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218: 11.3 CPU Module Max DC Power Requir
Page 221 and 222: Figure 68: module clocks Cobra - b
Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
Page 241: Copyright © 1993 Digital Equipment
Page 257 and 258: INDEX 21064 IEEE floating point con
Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261: STQC cycle, 144 STxC cycle, 144 STx
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