Sable CPU Module Specification

C.1 Introduction
APPENDIX C
COBRA SPECIFIC ( PRIVILEGED
ARCHITECTURE LIBRARY CODE ) PALCODE
In a family of machines both users and operating system implementers require functions
to be implemented consistently. When functions are implemented to a common
interface, the code that uses those functions can be used on several different implementations
without modification.
These functions range from the binary encoding of the instructions and data, to the
exception mechanisms and synchronization primitives. Some of these functions can
be cost effectively implemented in hardware, but several are impractical to implement
directly in hardware. These functions include low-level hardware support functions
such as translation buffer fill routines, interrupt acknowledge, and exception dispatch.
Also included is support for privileged and atomic operations that require
long instruction sequences such as Return from Exception or Interrupt (REI).
In the VAX architecture, these functions are generally provided by microcode. In the
21064, there is no microcode. However an architected interface to these functions
that will be consistent with other members of ALPHA family of machines is still
required. The Privileged Architecture Library Code (PALcode) is used to implement
these functions without resorting to a microcoded machine. The 21064 hardware development
group will provide and maintain a version of the PALcode for the 21064.
Module development groups will have to provide and maintain module specific modifications
to the PALcode.
C.2 PAL Environment
PALcode runs in an environment with privileges enabled, instruction stream mapping
disabled, and interrupts disabled. The enabling of privileges allows all functions
of the machine to be controlled. Disabling of instruction stream mapping allows
PALcode to be used to support the memory management functions (e.g., translation
buffer miss routines can not be run via mapped memory). PALcode can perform both
virtual and physical data stream references. The disabling of interrupts allows the
system to provide multi-instruction sequences as atomic operations. The PALcode
environment in the 21064 also includes 32 PAL temp registers which are accessible
only by PAL reserved move to/from processor register instructions.
Cobra Specific ( Privileged Architecture Library Code ) PALcode 223