Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Figure 81: Interprocessor Interrupt Request (IPIR-CSR11, offset = 0160) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 REQUEST NODE HALT INTERRUPT (RW) UNDEFINED (RW) REQUEST INT CPU (RW) 8 7 6 5 4 3 2 1 0 Figure 82: System Interrupt Clear Register (SIC-CSR12, offset = 0180) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 NODE HALT INTERRUPT CLEAR (RW) UNDEFINED (RO) SYSTEM EVENT CLEAR (RW) INTERVAL TIMER INTERRUPT CLEAR (RW) UNDEFINED (RW) System-bus ERROR INTERRUPT CLEAR (RW) UNDEFINED (RO) UNDEFINED (RO) Figure 83: Address Lock Register (ADLK-CSR13, offset = 01A0) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 LOCK ADDRESS (RO) LOCK ADDRESS VALID (RW) LOCK ADDRESS (RO) LOCK ADDRESS VALID (RW) 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 Sable CPU Module Register Reference Guide 221
Copyright © 1993 Digital Equipment Corporation. Figure 84: Miss Address Register Low (MADRL-CSR14, offset = 01C0) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 ADDRESS (RO) TRANSACTION TYPE (RO) MADR VALID (RO) TRANSACTION TYPE (RO) MADR VALID (RO) ADDRESS (RO) Figure 85: C4 Revision Register (CRR-CSR15, offset = 01E0) Disable CPU Node (RW) Forced Dcache Inv (RW) Enable I/O Retry (RW) Disable Duplicate Tag Parity Check (RW) Cache Interface Speed Bits (RW) CPU Mode (RO) Revision (RO) Disable CPU Node (RW) Forced Dcache Inv (RW) Enable I/O Retry (RW) Disable Duplicate Tag Parity Check (RW) Cache Interface Speed Bits (RW) CPU Mode (RO) Revision (RO) 8 7 6 5 4 3 2 1 0 6666555555555544 4444444433333333 3322222222221111 111111 3210987654321098 7654321098765432 1098765432109876 5432109876543210 222 Sable CPU Module Register Reference Guide
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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Page 183 and 184: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218: 11.3 CPU Module Max DC Power Requir
Page 221 and 222: Figure 68: module clocks Cobra - b
Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
Page 233: Copyright © 1993 Digital Equipment
Page 257 and 258: INDEX 21064 IEEE floating point con
Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261: STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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