Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Figure 77: Cobra-bus Error Register (CBE-CSR7, offset = 00E0) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 MADR VALID (RW) MISS COUNT H (RO) RETRY FAILED (WC) UNDEFINED H (WC) DATA PAR ERR LW7 ERR (RO) DATA PAR ERR LW5 ERR (RO) DATA PAR ERR LW3 ERR (RO) DATA PAR ERR LW1 ERR (RO) C/A PAR ERR LW3 ERR (RO) C/A PAR ERR LW1 ERR (RO) MISSED PAR ERR ON READ DATA - REQ H (RW) PAR ERR ON READ DATA - REQ H (RW) MISSED PAR ERR ON WRITE DATA - RESP H (RW) PAR ERR ON WRITE DATA - RESP H (RW) MISSED C/A PAR ERR (RW) C/A PAR ERR (RW) RESERVED DIAGNOSTIC H (RW) MADR VALID (RW) MISS COUNT (RO) RETRY FAILED (WC) WRITE DATA NOT ACKED (RW) C/A NOT ACKED (RW) DATA PAR ERR LW6 ERR (RO) DATA PAR ERR LW4 ERR (RO) DATA PAR ERR LW2 ERR (RO) DATA PAR ERR LW0 ERR (RO) C/A PAR ERR LW2 ERR (RO) C/A PAR ERR LW0 ERR (RO) MISSED PAR ERR ON READ DATA - REQ (RW) PAR ERR ON READ DATA - REQ (RW) MISSED ERR ON WRITE DATA - RESP (RW) PAR ERR ON WRITE DATA - RESP (RW) MISSED C/A ERR (RW) C/A PAR ERR (RW) RESERVED DIAGNOSTIC (RW) Sable CPU Module Register Reference Guide 219
Copyright © 1993 Digital Equipment Corporation. Figure 78: Cobra-bus Error Address Low (CBEAL-CSR8, offset = 0100) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 SBO (RO) SBO (RO) ADDRESS (RO) ADDRESS (RO) 8 7 6 5 4 3 2 1 0 Figure 79: Cobra-bus Error Address High (CBEAH-CSR9, offset = 0120) ODD WRITE MASKS (RO) SB1 (RO) COMMANDER ID (RO) TRANSACTION TYPE (RO) EXCHANGE ADDRESS (RO) SBO (RO) EVEN WRITE MASKS (RO) SB1 (RO) COMMANDER ID (RO) TRANSACTION TYPE (RO) EXCHANGE ADDRESS (RO) SBO (RO) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Figure 80: Processor Mailbox (PMBX-CSR10, offset = 0140) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 XMIT/RCV (RW) 220 Sable CPU Module Register Reference Guide 8 7 6 5 4 3 2 1 0
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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Page 181 and 182: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218: 11.3 CPU Module Max DC Power Requir
Page 221 and 222: Figure 68: module clocks Cobra - b
Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
Page 231: Copyright © 1993 Digital Equipment
Page 257 and 258: INDEX 21064 IEEE floating point con
Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261: STQC cycle, 144 STxC cycle, 144 STx
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