Sable CPU Module Specification
Sable CPU Module Specification Sable CPU Module Specification
Copyright © 1993 Digital Equipment Corporation. Figure 71: B-Cache Correctable Error (BCCE-CSR1, offset = 0020) EDC SYNDROME 3 (RO) EDC SYNDROME 1 (RO) BC EDC ERROR (RO) UNDEFINED (RO) CORRECTABLE ERROR H (RW) MISSED CORRECTABLE ERROR H (RW) EDC SYNDROME 2 (RO) EDC SYNDROME 0 (RO) BC EDC ERROR (RO) VALID (RO) DIRTY (RO) SHARED (RO) CONTROL BIT PARITY (RO) CORRECTABLE ERROR (RW) MISSED CORRECTABLE ERROR (RW) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Figure 72: B-Cache Correctable Error Address (BCCEA-CSR2, offset = 0040) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 TAG VALUE H (RO) TAG PARITY H (RO) B-CACHE MAP OFFSET H (RO) TAG VALUE (RO) TAG PARITY (RO) B-CACHE MAP OFFSET (RO) Sable CPU Module Register Reference Guide 215
Copyright © 1993 Digital Equipment Corporation. Figure 73: B-Cache Uncorrectable Error (BCUE-CSR3, offset = 0060) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 EDC SYNDROME 3 (RO) EDC SYNDROME 1 (RO) BC EDC ERROR (RO) UNCORRECTABLE ERROR H (RW) MISSED UNCORRECTABLE ERROR H (RW) PARITY ERROR H (RW) MISSED PAR ERROR H (RW) EDC SYNDROME 2 (RO) EDC SYNDROME 0 (RO) BC EDC ERROR (RO) VALID (RO) DIRTY (RO) SHARED (RO) CONTROL BIT PARITY (RO) UNCORRECTABLE ERROR (RW) MISSED UNCORRECTABLE ERROR (RW) PARITY ERROR (RW) MISSED PAR ERROR (RW) Figure 74: B-Cache Uncorrectable Error Address (BCUEA-CSR4, offset = 0080) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 TAG VALUE H (RO) TAG PARITY H (RO) PREDICTED TAG PAR H (RO) B-CACHE MAP OFFSET H (RO) TAG VALUE (RO) TAG PARITY (RO) PREDICTED TAG PAR (RO) B-CACHE MAP OFFSET (RO) 216 Sable CPU Module Register Reference Guide
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Copyright © 1993 Digital Equipment Corporation.<br />
Figure 73: B-Cache Uncorrectable Error (BCUE-CSR3, offset = 0060)<br />
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1<br />
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />
EDC SYNDROME 3 (RO)<br />
EDC SYNDROME 1 (RO)<br />
BC EDC ERROR (RO)<br />
UNCORRECTABLE ERROR H (RW)<br />
MISSED UNCORRECTABLE ERROR H (RW)<br />
PARITY ERROR H (RW)<br />
MISSED PAR ERROR H (RW)<br />
EDC SYNDROME 2 (RO)<br />
EDC SYNDROME 0 (RO)<br />
BC EDC ERROR (RO)<br />
VALID (RO)<br />
DIRTY (RO)<br />
SHARED (RO)<br />
CONTROL BIT PARITY (RO)<br />
UNCORRECTABLE ERROR (RW)<br />
MISSED UNCORRECTABLE ERROR (RW)<br />
PARITY ERROR (RW)<br />
MISSED PAR ERROR (RW)<br />
Figure 74: B-Cache Uncorrectable Error Address (BCUEA-CSR4, offset = 0080)<br />
6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1<br />
3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0<br />
TAG VALUE H (RO)<br />
TAG PARITY H (RO)<br />
PREDICTED TAG PAR H (RO)<br />
B-CACHE MAP OFFSET H (RO)<br />
TAG VALUE (RO)<br />
TAG PARITY (RO)<br />
PREDICTED TAG PAR (RO)<br />
B-CACHE MAP OFFSET (RO)<br />
216 <strong>Sable</strong> <strong>CPU</strong> <strong>Module</strong> Register Reference Guide
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