Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Figure 69: Module Layup (reference) L1 L2 L3 L4 L5 L6 L7 L8 210 Physical and Electrical Characteristics Pads .005 1 oz + .003/-.001 68 (6.0 MIL FLW) ohm signal .008 + .003/-.002 Gnd (1 oz) .009 +.003/-.002 68 (50 mil FLW) 48 (11 mil FLW) ohm signal/clock .010 +.003/-.003 68 (50 mil FLW) ohm signal/clock .009 +.003/-.002 3.3V and 5.0V .008 + .003/-.002 68 (6.0 MIL FLW) Ohm signal .005 +.003/-.001 Pads (1/2 oz (.0014 min finished)) (1 oz) (1 oz) (1/2 oz (.0014 min finished)) (1 oz) (1 oz) [yuryan.cpu]layup_decw.doc
APPENDIX A ALPHA ARCHITECTURE OPTIONS SUPPORTED • Cycle counter - RCC • 8 KB virtual page size • 4 GB physical memory address space reserved of which the Sable CPU will support a maximum of 2GB of physical memory. (Cacheable) • 10 GB physical I/O address space reserved (non-Cacheable) • 976.5625 microseconds interval-timer frequency Alpha Architecture Options Supported 211
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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Page 173 and 174: Copyright © 1993 Digital Equipment
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Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261: STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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