Sable CPU Module Specification

Table 85 (Cont.): System bus AC and DC Characteristics
Copyright © 1993 Digital Equipment Corporation.
Parameter Description Min Max Units Notes
AC Characteristics
Tcp Clock Period 24 40 ns
Tcw Tphi Clock high or low width @Tcpmin 12.0 20.0 ns
Tmskh module-to-module TPHI1 to TPHI1 skew 6 0 6 1.0 ns
Tmskl module-to-module TPHI1_L to TPHI1_L skew 6 0 6 1.0 ns
Tmsk module-to-module TPHI1 to TPHI1_L skew 6 0 6 1.0 ns
6 0 6 0.5 ns
Taskh ASIC-to-ASIC (same module) TPHI1 to
TPHI1 skew
Taskl ASIC-to-ASIC (same module) TPHI1_L to
TPHI1_L skew
6 0 6 0.5 ns
Tcko TPHI1 to System bus BD8TRP output high
or low
3.0 6.0 ns
Tsu System bus input setup time high or low
to TPHI
2.0 - ns
Thld TPHI-to-System bus input hold high or low 1.0 - ns
Thz TPHI-to-System bus output off time 3.5 6 ns
Tpup TPHI1_L rising to System bus OD output
@Voh = 2.4V, rising not critical
4.0 21 ns
Tpuc TPHI1_L rising to System bus rising edge
critical OD output @Voh = 2.4v
4.0 18 ns
Cp BD8TRP or BD4TRP Signal pin capacitance
in 299 PGA
2 5 pF
Cpod 48ma open drain Signal pin capacitance
in 299 PGA
3 8 pF
The module is an 8-layer module with a signal Z0 of 68 67 ohms with a minimum
width 5-mil line and minimum 9-mil spaces and a clock Z0 of 48 +6/-5 ohms on
layer four only, with a minimum width 11-mil line and minimum 20-mil spaces. Via
diameter is typically 15 mils, but 10 mil vias are used also. Figure 69 shows the
module layer construction.
Physical and Electrical Characteristics 209