Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. 1.1 The 21064 CPU Chip The 21064 CPU chip is a 431-pin PGA CMOS-4 chip that contains approximately 2.3 million transistors. The chip is a super-scaler, super-pipelined implementation of the Digital AXP Architecture. The DECchip 21064-A275 has basically the same pinning, but is a CMOS-5 chip containing a larger Icache and Dcache. Figure 3 shows a block diagram of the CPU chip and Section 1.2 provides a brief description of the architecture. Figure 3: 21064 CPU Chip Block Diagram Branch History Table EBOX Multiplier Adder Shifter Logic Box IRF Write Buffer Address Generator ICACHE IBOX Prefetcher Resource Conflict PC Calculation ITB Pipeline Control ABOX DCACHE TAG DATA DTB TAG DATA 4 CPU Module Components and Features FBOX Multiplier/ Adder Divider FRF Load Silo BIU Address Bus Data Bus (128 bits) External Cache Control External System Interface LJ-02107-TI0
1.2 The Alpha AXP Architecture Copyright © 1993 Digital Equipment Corporation. The Alpha AXP architecture is a 64-bit load/store RISC architecture designed with particular emphasis on speed, multiple instruction issue, multiple processors, and software migration from VAX/VMS and MIPS/ULTRIX. All registers are 64 bits in length and all operations are performed between 64-bit registers. All instructions are 32 bits in length. Memory operations are either loads or stores. All data manipulation is done between registers. The Alpha AXP architecture supports the following data types: • 8-, 16-, 32- and 64-bit integers • IEEE 32-bit and 64-bit floating point formats • VAX computer 32-bit and 64-bit floating point formats In the Alpha AXP architecture, instructions interact with each other only by one instruction writing to a register or memory location and another instruction reading from that register or memory location. This use of resources makes it easy to build implementations that issue multiple cycles every CPU cycle. The 21064 uses a set of subroutines, called privileged architecture library code (PALcode), that is specific to a particular Alpha AXP operating system implementation and hardware platform. These subroutines provide operating system primitives for context switching, interrupts, exceptions, and memory management. These subroutines can be invoked by hardware or CALL_PAL instructions. CALL_PAL instructions use the function field of the instruction to vector to a specified subroutine. PALcode is written in standard machine code with some implementation-specific extensions to provide direct access to low-level hardware functions. PALcode supports optimizations for multiple operating systems, flexible memory management implementations, and multi-instruction atomic sequences. The Alpha AXP architecture does byte shifting and masking with normal 64-bit register-to-register instructions; it does not include single byte load/store instructions. The software implementor must determine the precision of arithmetic traps. For a complete introduction to the Alpha AXP architecture, see the Alpha Architecture Handbook. CPU Module Components and Features 5
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7 and 8: 7.1.1 Exception Handling ..........
Page 9 and 10: 11.4 Environmental Specifications -
Page 11 and 12: 25 MM_CSR .........................
Page 13 and 14: 27 Base Addresses for CSRs . . . ..
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19 and 20: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 21: Copyright © 1993 Digital Equipment
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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