Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
11.4.2.1 Storage
10% to 95%
11.4.2.2 Operating
10% to 95% non-condensing at 304 meters of altitude.
11.4.3 Altitude
Reference: Standard Atmosphere, Standard Gravity.
11.4.3.1 Storage
The module is not mechanically or electrically damaged at altitudes up to 4.9 Km
11.4.3.2 Operating Altitude
The module can be operated up to 2.4 Km.
11.4.4 Airflow
Airflow must be at least 91.44 linear meters/minute.
11.4.5 Contamination
The module must be stored and used in a non-caustic environment.
11.4.6 Mean Time Between Failure (MTBF) Rate
The MTBF for the CPU module is TBD hours.
11.4.7 Electrical Characteristics
This module connects to the System bus backplane to an MCA 240-pin connector,
two 299-pin PGA gate arrays, and one 44-pin PLCC arbitration gate array. System
bus protocol signals are TTL levels, and backplane clocks are PECL levels.
11.4.7.1 AC References
System bus signals are driven relative to a TPHI1 or TPHI1_L rising edge. Receivers
must latch these signals using a TPHI1 or TPHI1_L rising edge, respectively.
11.4.8 Clock Description
The module receives two differential clock signal pairs and AC couples them to two
PECL to CMOS level converter chips (DC277BA DEC PN 21-36105-02). The four
clock signals are routed on layer 4 etch from the connector pins and are 50mm using
a 50 ohm etch impedance. Each of the four PECL clock signals connects to a 50 ohm
termination (Thevenin - 82 ohms and 120 ohms - 5%) and two 680pF capacitors. etch
from the connector pins and are 50mm using a 48 ohm etch impedance (12/20 lines).
204 Physical and Electrical Characteristics