Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Table 83 (Cont.): MCA44 J3 Side 1 Side 2 18 GND 40 GND 19 VCC_3V H 41 VCC_3V H 20 VCC_3V H 42 VCC_3V H 21 VCC_3V H 43 VCC_3V H 22 GND 44 GND 202 Physical and Electrical Characteristics
11.3 CPU Module Max DC Power Requirement Copyright © 1993 Digital Equipment Corporation. The power requirements shown in Table 84 assume a 24ns System bus cycle. Table 84: CPU Power Requirements Configuration EV Clock 3.3V ± 5% DC 5V ± 5% DC Speed (ns) Max (amps) Max (amps) B2020-AA 5.26 14.5 13.0 B2024-AA 3.64 0.0 25.0 11.4 Environmental Specifications - Class B modified 11.4.1 Temperature 11.4.1.1 Storage Range -40 degrees Celsius to +66 degrees Celsius. Before operating a module which is at a temperature beyond the operating range, that module must first be brought to an environment within the operating range, and then allowed to stabilize for a reasonable length of time. (Five or more minutes, depending on air circulation.) 11.4.1.2 Operating Range 5 degrees Celsius to 35 degrees Celsius environment with 10 degrees Celsius rise from inlet to outlet air. The enclosure is Class B rated with a 10 to 40 degrees Celsius environment and 10 degrees Celsius rise from inlet to outlet with a 20-80% noncondensing relative humidity. De-rate the maximum operating temperature by 1.82 degrees Celsius for each 1000 meters of altitude above sea level. Reference: Standard Atmosphere, Standard Gravity. 11.4.2 Relative Humidity Physical and Electrical Characteristics 203
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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Page 165 and 166: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
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Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
Page 257 and 258: INDEX 21064 IEEE floating point con
Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261: STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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