Sable CPU Module Specification

More documents

Recommendations

Info

$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

10.9 Performance Counters Copyright © 1993 Digital Equipment Corporation. There are two performance counters on the DECchip 21064 processor. They can be configured to count various processor internal events. Externally these have been connected to pulldown resistors on the CPU module. 10.10 Brain Dead Module Errors When the reset signal going to the DECchip 21064 processor deasserts, the processor begins reading serial ROM 1. This continues until the complete ROM had been read which causes the Serial ROM 1 Read indicator of the D-bus microcontroller to be asserted. As there is a fixed time between when reset deasserts by adding a time out between D-bus micro powerup and Serial ROM 1 Read, it is possible to signal to the Operator Control Panel via the Serial Control Bus that the DECchip 21064 processor is dead. Depending on the firmware in the serial ROMs the code running in the D-bus micro may watch for one or all serial ROM read signals to be asserted before indicating CPU module failure. Table 80: Kernel Survivability Matrix Node Cobrabus OSC Failing Element DECchip 21064 OSC DECchip 21064† 3.3V Survivability CPU X D-bus micro clock also dead so no ability to signal failure. CPU X D-bus micro can detect this as Clock/Voltage Detect is clear, serial ROM read signals not asserted before time out period, and DECchip 21064 processor Resetting asserted. When occurs signal OCP and log in EEPROM. CPU X D-bus micro can detect this as serial ROM read signals not asserted by time out of TBDms. Can communicate with OCP and log in CPU module EEPROM. CPU X Possible to detect if problem exists in CPU1 3.3V detect circuit. If 3.3V actually failed, as all 3.3V comes from the backplane CPU0 would detect failure and CRESET L would assert taking D-bus micro reset with it. CRESET(A D-bus micro reset). Send to OCP and log in EEPROM. †DECchip 21064 unable to finish reading serial ROM(s) Once the Serial ROMs have been read, the D-bus micro will enter into dialogue with the DECchip 21064 processor over the D-bus. Thus if the DECchip 21064 processor is unable to make it to the FEPROMs on the I/O module it is able to log the errors and communicate them to the OCP. Overview of the CPU testability features 195
CHAPTER 11 PHYSICAL AND ELECTRICAL CHARACTERISTICS 11.1 CPU Module Physical Specification There are three attached components to the Sable CPU module which should be noted. Two ejectors are attached in two corners to facilitate insertion and removal of the modules. A stiffener is attached along the edge with the ejectors to reduce bowing and add rigidity during insertion and removal There may be an air flow accelerator attached to the module to direct air flow to the more critical components. 11.2 SABLE CPU CONNECTOR PINNING Table 81: MCA240 J5 SIDE 1 SIDE 2 1 CADH 121 2 CADH 122 CADH 3 GND 123 GND 4 CADH 124 CADH 5 CADH 125 CADH 6 CADH 126 CADH 7 GND 127 GND 8 CADH 128 CADH 9 CADH 129 CADH 10 CADH 130 CADH 11 GND 131 GND 12 CADH 132 CADH 13 CADH 133 CADH Physical and Electrical Characteristics 197
Page 1 and 2:
Sable CPU Module Specification This
Page 3 and 4:
CONTENTS Preface ..................
Page 5 and 6:
3.9.6 Data Cache Address Register (
Page 7 and 8:
7.1.1 Exception Handling ..........
Page 9 and 10:
11.4 Environmental Specifications -
Page 11 and 12:
25 MM_CSR .........................
Page 13 and 14:
27 Base Addresses for CSRs . . . ..
Page 15 and 16:
Preface Scope and Organization of t
Page 17 and 18:
Copyright © 1993 Digital Equipment
Page 19 and 20:
CHAPTER 1 CPU MODULE COMPONENTS AND
Page 21 and 22:
Page 23 and 24:
1.2 The Alpha AXP Architecture Copy
Page 25 and 26:
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
Page 35 and 36:
Page 37 and 38:
Page 39 and 40:
Page 41 and 42:
Page 43 and 44:
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
Page 59 and 60:
Page 61 and 62:
Page 63 and 64:
Page 65 and 66:
Page 67 and 68:
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Page 87 and 88:
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
Page 101 and 102:
Page 103 and 104:
Figure 41: B-Cache Control Register
Page 105 and 106:
Table 28 (Cont.): B-Cache Control R
Page 107 and 108:
Table 28 (Cont.): B-Cache Control R
Page 109 and 110:
Page 111 and 112:
Page 113 and 114:
Page 115 and 116:
Page 117 and 118:
Page 119 and 120:
Page 121 and 122:
4.3.1 Duplicate Tag Error Register
Page 123 and 124:
4.5 Lack of Cache Block Prefetch Co
Page 125 and 126:
Table 37: System-bus Control Regist
Page 127 and 128:
4.7.2 System-bus Error Register - C
Page 129 and 130:
Table 38: System-bus Error Register
Page 131 and 132:
Table 38 (Cont.): System-bus Error
Page 133 and 134:
4.7.3 System-bus Error Address Low
Page 135 and 136:
Page 137 and 138:
4.8 Multiprocessor Configuration CS
Page 139 and 140:
4.9 System Interrupt Clear Register
Page 141 and 142:
4.10 Address Lock Register - CSR13
Page 143 and 144:
4.11 Miss Address Register - CSR14
Page 145 and 146:
Table 46 (Cont.): C4 Revision Regis
Page 147 and 148:
Table 48 (Cont.): Interval Timer In
Page 149 and 150:
Table 50: D-bus Microcontroller Clo
Page 151 and 152:
Figure 58: Granting Order rule 4 CP
Page 153 and 154:
Page 155 and 156:
Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158:
Table 57: CPU EEPROM Defaults Locat
Page 159 and 160: Copyright © 1993 Digital Equipment
Page 209: Copyright © 1993 Digital Equipment
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218: 11.3 CPU Module Max DC Power Requir
Page 221 and 222: Figure 68: module clocks Cobra - b
Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
Page 257 and 258: INDEX 21064 IEEE floating point con
Page 259 and 260: Icache, 59 ICCSR, 19 IEEE Floating
Page 261:
STQC cycle, 144 STxC cycle, 144 STx
show all

Sable CPU Module Specification

Create successful ePaper yourself

Delete template?

Save as template?