Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Figure 1: Sable CPU Module Block Diagram DATA_A ADDR SERIAL ROM INV_ADR ADDR SERIAL CONTROL BUS SERIAL CTRL BUS INTERFACE TAG_INDEX TAG_INDEX CHECK TAG 21064 CPU Chip B-Cache TAG STORE DATA STORE LW0, LW2 PROC OSC CLK DETECT DATA EVEN SLICE ODD SLICE System bus interface (SBI) SYSTEM BUS 2 CPU Module Components and Features to Memory module, IO module, and operator control panel LW1, LW3 Arbitor To memory module, and IO module KN450_BLOCK.DOC PS @ 55%
Copyright © 1993 Digital Equipment Corporation. Many of the CPU module’s subsystems are incorporated into a single ASIC chip, the C4 chip, developed in the AVS Engineering Group. These subsystems include the Write Merge Buffer, Duplicate Tag Store, System-bus interface, and arbitrator, the Address Lock, and the control machines for B-Cache management and System-bus Snooping. Figure 2 shows a block diagram of the C4 chip. Figure 2: C4 Chip Block Diagram 512KB Cache Configuration Shown TAG ADDRESS ADDRESS ADDRESS TAG TAG COMPARITOR ECC OR ECC DATA OR DATA DATA OR DATA ECC GEN/CHECK TAG PARITY GEN/CHECK PRIMARY CACHE BACK MAP ADDR B-CACHE & C-bus STATUS & CONTROL REGISTERS -ADDRESS LOCK -INTERPROC INTER -PROC MAILBOX -NON-MASK INTR C-BUS -CONTROL/STATUS -ERROR B-CACHE -CONTROL/STATUS -ERROR REGS -TAG STORE ERRORS WRITE MERGE BUFFER WRITE MERGE BUFFER HOLD INVALIDATE CONTROL TAG PARITY PREDICTOR Cobra-bus ARBITRATOR DATA HOLD Cache Line Control Command Generation Command Detection CPU Module Components and Features 3 ADR HOLD C-bus Interface
Page 1 and 2: Sable CPU Module Specification This
Page 3 and 4: CONTENTS Preface ..................
Page 5 and 6: 3.9.6 Data Cache Address Register (
Page 7 and 8: 7.1.1 Exception Handling ..........
Page 9 and 10: 11.4 Environmental Specifications -
Page 11 and 12: 25 MM_CSR .........................
Page 13 and 14: 27 Base Addresses for CSRs . . . ..
Page 15 and 16: Preface Scope and Organization of t
Page 17 and 18: Copyright © 1993 Digital Equipment
Page 19: CHAPTER 1 CPU MODULE COMPONENTS AND
Page 23 and 24: 1.2 The Alpha AXP Architecture Copy
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Copyright © 1993 Digital Equipment
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
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Table 48 (Cont.): Interval Timer In
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Table 50: D-bus Microcontroller Clo
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Figure 58: Granting Order rule 4 CP
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Table 54 (Cont.): BIU_CTL Field Des
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Table 57: CPU EEPROM Defaults Locat
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CHAPTER 11 PHYSICAL AND ELECTRICAL
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Table 81 (Cont.): MCA240 J5 SIDE 1
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Table 82 (Cont.): MCA44 J1 Side 1 S
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11.3 CPU Module Max DC Power Requir
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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