Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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CHAPTER 10 OVERVIEW OF THE CPU TESTABILITY FEATURES This chapter contains an overview of the hooks added to the CPU module to provide an easier means to verify/debug them. The intended audience is diagnostic engineers; however anyone involved in the manufacture/debug of the module may find it useful. 10.1 Bus Verification 10.1.1 Address As part of the B-Cache Init Mode (BCC register) the address bus is looped back through the C4 onto the address bus. Thus the addresses presented to the C4 will be returned as read data to the processor. This enables the serial ROM firmware to verify the integrity of the address bus. It should be noted that whenever a C4 CSR is accessed the data is broadcast on the Cobra-bus, therefore if there is a failure on the Cobra-bus these cycles could become corrupted. 10.1.2 Data By reading and writing arbitrary patterns to the mailbox register it is possible to verify the integrity of the data bus all the way to the C4. It should be noted that whenever a C4 CSR is accessed the data is broadcast on the Cobra-bus, therefore if there is a failure on the Cobra-bus these cycles could become corrupted. 10.2 C4 EDC Generators The EDC Generator in the C4 can be tested quite simply by reading and writing arbitrary patterns to the Processor Mailbox register. When this or any CSR is read (locally CPU CSR’s only) the data returned is not only presented on the low order quadword of the cache block, but also every other quadword. This way all EDC generators can be verified by reading both low and high order quadwords of a given CPU module local CSR. Overview of the CPU testability features 193

Copyright © 1993 Digital Equipment Corporation. 10.3 C4 EDC Checkers The EDC Checkers/correctors in the C4 can be verified by writing various data patterns in the B-Cache with correct and incorrect EDC values. (Using FORCE EDC/CONTROL BCC functionallity) Then forcing them to be writing to memory, using allocation invalid mode or some other means to victimize dirty cache blocks. 10.4 DECchip 21064 EDC Checkers The EDC Checkers in DECchip 21064 can be verified by writing various data patterns in the B-Cache with correct and incorrect EDC values, (Using FORCE EDC/CONTROL BCC functionallity) and then reading them in force hit mode. 10.5 DECchip 21064 EDC Generators The EDC Generators in DECchip 21064 can be verified by enabling EDC mode and writing various data patterns that are known to miss the B-Cache. 10.6 C4 Cobra-bus Probe Predicted Tag Parity Generator This parity generator calculates the parity of the normal address portion presented on the Cobra-bus across the field of bits relating to the address bits stored in the modules tag store. By causing various Cobra-bus cycles to occur at various addresses, resulting in errors, this parity tree can be completely verified. 10.7 B-Cache Data Store Verification The B-Cache Data Store can be verified by setting the DECchip 21064 processor in force hit mode on the B-Cache (EV-BIU_CTL). This enables the user to access the B-Cache as if it was just a physically contiguous section of memory starting at 0 and ending at the limits of its size. (It is also ghosted on up through the complete DECchip 21064 address space.) Arbitrary patterns can be read and written. When testing the EDC RAMs in the B-Cache Data Store, it is advised to use the B-Cache Init Mode with the FORCE EDC/CONTROL functionallity. This allows the user to simply write arbitrary patterns in the EDC RAMs without regard to the actual EDC code. 10.8 B-Cache Tag/Control Store Verification The B-Cache Tag and Tag Control Stores can be verified by writing different patterns into each Tag/Tag Control Store location. This is accomplished using the B-Cache Init Mode. (Refer to the BCC register for details.) When this mode is enabled, by prudently choosing the addresses read, the user can completely test the tag store. Using the FORCE EDC/CONTROL functions, all the Tag Control Store locations can also be tested. 194 Overview of the CPU testability features

Copyright © 1993 Digital Equipment Corporation.<br />

10.3 C4 EDC Checkers<br />

The EDC Checkers/correctors in the C4 can be verified by writing various data<br />

patterns in the B-Cache with correct and incorrect EDC values. (Using FORCE<br />

EDC/CONTROL BCC functionallity) Then forcing them to be writing to memory,<br />

using allocation invalid mode or some other means to victimize dirty cache blocks.<br />

10.4 DECchip 21064 EDC Checkers<br />

The EDC Checkers in DECchip 21064 can be verified by writing various data<br />

patterns in the B-Cache with correct and incorrect EDC values, (Using FORCE<br />

EDC/CONTROL BCC functionallity) and then reading them in force hit mode.<br />

10.5 DECchip 21064 EDC Generators<br />

The EDC Generators in DECchip 21064 can be verified by enabling EDC mode and<br />

writing various data patterns that are known to miss the B-Cache.<br />

10.6 C4 Cobra-bus Probe Predicted Tag Parity Generator<br />

This parity generator calculates the parity of the normal address portion presented<br />

on the Cobra-bus across the field of bits relating to the address bits stored in the<br />

modules tag store. By causing various Cobra-bus cycles to occur at various addresses,<br />

resulting in errors, this parity tree can be completely verified.<br />

10.7 B-Cache Data Store Verification<br />

The B-Cache Data Store can be verified by setting the DECchip 21064 processor in<br />

force hit mode on the B-Cache (EV-BIU_CTL). This enables the user to access the<br />

B-Cache as if it was just a physically contiguous section of memory starting at 0<br />

and ending at the limits of its size. (It is also ghosted on up through the complete<br />

DECchip 21064 address space.) Arbitrary patterns can be read and written.<br />

When testing the EDC RAMs in the B-Cache Data Store, it is advised to use the<br />

B-Cache Init Mode with the FORCE EDC/CONTROL functionallity. This allows the<br />

user to simply write arbitrary patterns in the EDC RAMs without regard to the<br />

actual EDC code.<br />

10.8 B-Cache Tag/Control Store Verification<br />

The B-Cache Tag and Tag Control Stores can be verified by writing different patterns<br />

into each Tag/Tag Control Store location. This is accomplished using the B-Cache<br />

Init Mode. (Refer to the BCC register for details.) When this mode is enabled, by<br />

prudently choosing the addresses read, the user can completely test the tag store.<br />

Using the FORCE EDC/CONTROL functions, all the Tag Control Store locations can<br />

also be tested.<br />

194 Overview of the <strong>CPU</strong> testability features

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