Sable CPU Module Specification

Table 79: LDQ Data Format Description
Field Description
Copyright © 1993 Digital Equipment Corporation.
63:34 ADDRESS FIELD H [ read-only ]
Contains the C/A address field for this cycle. Which is equal to the address of the data reference
of the LDQ.
33:32 SBO [ read-only ]
These bits should be zero.
31:2 ADDRESS FIELD L [ read-only ]
Contains the C/A address field for this cycle. Which is equal to the address of the data reference
of the LDQ.
1:0 SBO [ read-only ]
These bits should be zero.
9.3 Duplicate Tag Store Initialization
The Duplicate Tag Store will be reset to all zero’s and correct parity on powerup. No
user intervention is required.
9.4 System-bus Interface Initialization
1. The System-bus Control Register should be initialized so that System-bus parity
checking is enabled and all other write-able bits cleared. As well as setting the
SELECT DRACK and 2nd QW SELECT bits to the appropriate values.
2. All error bits in the System-bus Error Register should be cleared.
3. Retry should be enabled and speed-bits set to the appropriate values.
9.5 CPU clocks and reset
System-bus reset will assert asynchronously with respect to the System-bus clocks,
and will deassert synchrounously with PHI1. The CPU module has been designed
to expect the clocks to be free running during reset. Refer to Cobra System Bus
Specification and Section 4.15 for further details.
9.6 Power-up Sequence
The system power supply is required to bring 3.3V up before 5V. If 3V goes below
regulation, the DCOK signal to EV will be deasserted.
CPU Powerup And Initialization 191