Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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CHAPTER 9 CPU POWERUP AND INITIALIZATION This chapter describes the behavior of the CPU module when System-bus RESET_L deasserts. The initial states of the processor and module registers are described. 9.1 Processor Initialization 9.1.1 Internal Processor Registers Refer to Section C.6 for a description of the processors internal registers powerup state. 9.1.2 Internal JSR stack Refer to Section C.6 for a discussion regarding the initialization of the jsr stack via PALcode. 9.2 B-Cache Initialization B-Cache Initialization is performed by the DECchip 21064 processor. This is accomplished as follows: 1. Write to CSR15 to configure desired values for speed bits and enable CBUS retry. 2. Set Cache Size set to the appropriate value in BCC 3. Clear BC_EN in the EV BIU_CTL Register 4. Clear Fill Wrong Parity and disable tag and tag control store parity checking by clearing the ENB TAG & DUP TAG PAR CHK bits in the BCC register. 5. Set EDC H, EDC L, and SHARED, DIRTY, VALID (BCC) to desired values. 6. Set ENABLE B-CACHE INIT (H) in the BCC Register (,) 7. Set ENABLE ALLOCATE (H) in the BCC Register (,) 8. Perform LDQ from Bcache Init space starting at address 1.0000.0000 address range and continue up in 32 byte increments until the address range equal to the size of the cache in the system has been exhausted. CPU Powerup And Initialization 189

Copyright © 1993 Digital Equipment Corporation. The B-Cache Control Store will then contain the values for Shared, Dirty, and Valid provided in the BCC register before initialization. The B-Cache Tag Store will contain a Tag equivalent to the high order address bits specified during the 9th step above. Each quadword in the B-Cache Data Store of a particular cache block will contain data identical to the data returned during the read (format indicated in Section 9.2.1. Once the B-Cache RAMS have been initialized the B-Cache Control/Status Register should be set to 0000.01C5.0000.01C5 for a 1MB backup cache module, or 8000.01C5.8000.01C5 for a 4MB backup cache module. This configures the module as follows: 4-meg CACHE SIZE set/cleared BCC FORCE EDC/CONTROL Cleared BCC ENB B-CACHE INIT Cleared BCC ENB B-CACHE COND I/O UPDATES Cleared BCC ENB B-CACHE EDC CHK Set BCC ENB B-CACHE CORRECTION Set BCC ENB B-CACHE COR ERR INTERRUPT Set BCC FILL WRONG DUP TAG STORE PAR Cleared BCC FILL WRONG CONTROL PAR Cleared BCC FILL WRONG TAG PAR Cleared BCC ENB TAG and DUP TAG PAR CHK Set BCC FORCE FILL SHARED Cleared BCC ENABLE ALLOCATE Set BCC All error bits in the B-Cache Correctable, Uncorrectable, and Duplicate Tag Store Error Registers should be cleared. 9.2.1 LDQ Data Format - BCC ENABLE B-CACHE INIT Set Figure 66: LDQ Data Format (LDQ_DF) 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 ADDRESS FIELD H (RO) SBO (RO) ADDRESS FIELD L (RO) SBO (RO) 190 CPU Powerup And Initialization 8 7 6 5 4 3 2 1 0

Copyright © 1993 Digital Equipment Corporation.<br />

The B-Cache Control Store will then contain the values for Shared, Dirty, and Valid<br />

provided in the BCC register before initialization. The B-Cache Tag Store will contain<br />

a Tag equivalent to the high order address bits specified during the 9th step above.<br />

Each quadword in the B-Cache Data Store of a particular cache block will contain<br />

data identical to the data returned during the read (format indicated in Section 9.2.1.<br />

Once the B-Cache RAMS have been initialized the B-Cache Control/Status Register<br />

should be set to 0000.01C5.0000.01C5 for a 1MB backup cache module, or<br />

8000.01C5.8000.01C5 for a 4MB backup cache module. This configures the module<br />

as follows:<br />

4-meg CACHE SIZE set/cleared BCC<br />

FORCE EDC/CONTROL Cleared BCC<br />

ENB B-CACHE INIT Cleared BCC<br />

ENB B-CACHE COND I/O UPDATES Cleared BCC<br />

ENB B-CACHE EDC CHK Set BCC<br />

ENB B-CACHE CORRECTION Set BCC<br />

ENB B-CACHE COR ERR INTERRUPT Set BCC<br />

FILL WRONG DUP TAG STORE PAR Cleared BCC<br />

FILL WRONG CONTROL PAR Cleared BCC<br />

FILL WRONG TAG PAR Cleared BCC<br />

ENB TAG and DUP TAG PAR CHK Set BCC<br />

FORCE FILL SHARED Cleared BCC<br />

ENABLE ALLOCATE Set BCC<br />

All error bits in the B-Cache Correctable, Uncorrectable, and Duplicate Tag Store<br />

Error Registers should be cleared.<br />

9.2.1 LDQ Data Format - BCC ENABLE B-CACHE INIT Set<br />

Figure 66: LDQ Data Format (LDQ_DF)<br />

6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1<br />

3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9<br />

ADDRESS FIELD H (RO)<br />

SBO (RO)<br />

ADDRESS FIELD L (RO)<br />

SBO (RO)<br />

190 <strong>CPU</strong> Powerup And Initialization<br />

8 7 6 5 4 3 2 1 0

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