Sable CPU Module Specification

CHAPTER 9
CPU POWERUP AND INITIALIZATION
This chapter describes the behavior of the CPU module when System-bus RESET_L
deasserts. The initial states of the processor and module registers are described.
9.1 Processor Initialization
9.1.1 Internal Processor Registers
Refer to Section C.6 for a description of the processors internal registers powerup
state.
9.1.2 Internal JSR stack
Refer to Section C.6 for a discussion regarding the initialization of the jsr stack via
PALcode.
9.2 B-Cache Initialization
B-Cache Initialization is performed by the DECchip 21064 processor. This is accomplished
as follows:
1. Write to CSR15 to configure desired values for speed bits and enable CBUS retry.
2. Set Cache Size set to the appropriate value in BCC
3. Clear BC_EN in the EV BIU_CTL Register
4. Clear Fill Wrong Parity and disable tag and tag control store parity checking by
clearing the ENB TAG & DUP TAG PAR CHK bits in the BCC register.
5. Set EDC H, EDC L, and SHARED, DIRTY, VALID (BCC) to desired values.
6. Set ENABLE B-CACHE INIT (H) in the BCC Register (,)
7. Set ENABLE ALLOCATE (H) in the BCC Register (,)
8. Perform LDQ from Bcache Init space starting at address 1.0000.0000 address
range and continue up in 32 byte increments until the address range equal to
the size of the cache in the system has been exhausted.
CPU Powerup And Initialization 189