Sable CPU Module Specification
Sable CPU Module Specification Sable CPU Module Specification
Table 76: B-Cache Uncorrectable Errors Copyright © 1993 Digital Equipment Corporation. Transaction Causing Probe Access Reason Error Recovery Activity System-bus READ (Dirty) or Exchange (Read Dirty) System-bus READ / EX- CHANGE Dirty System-bus Write Probe If HIT System-bus write data has either bad parity or has CUCERR L Assert System-bus CUCERR L with the data returned to the System-bus. The B-Cache Uncorrectable Error (BCUE) and B-Cache Uncorrectable Error Address Registers (BCUEA) are frozen and the UNCOR- RECTABLE ERROR bit set. The B-Cache is written with BAD EDC. DECchip 21064 Read Block Victim Processing The System-bus C_ERR L signal is asserted, the victim written to memory coincident with the assertion of CUCERR L and the cycle is acknowledged to the processor with HARD_ ERROR. The B-Cache is not updated, and B-Cache allocation is disabled. The BCUE and BCUEA registers are frozen and the UNCORRECTABLE ERROR bit set. System-bus returned data with bad System-bus parity or CUCERR L asserted with read data DECchip 21064 Write Block Victim Processing / Shared Masked Write The System-bus C_ERR L signal is asserted, bad "second" read data from the System-bus is returned to the processor, bad "second" data from the System-bus is written with "bad EDC" in the B-Cache, The BCUE and BCUEA registers are frozen and the UNCORRECTABLE ERROR bit set, processor is acknowledged with HARD_ERROR. The System-bus C_ERR L signal is asserted, the victim / shared write is written to memory coincident with the assertion of CUCERR L, and the B-Cache is updated with the new data. In the case of a shared masked write, the B- Cache longwords with failing EDC that are not updated by the processor write, will not be rewritten. The BCUE and BCUEA registers are frozen and the UNCORRECTABLE ERROR bit set. Fault Management/Error Recovery 185
Copyright © 1993 Digital Equipment Corporation. Table 76 (Cont.): B-Cache Uncorrectable Errors Transaction Causing Probe Access Reason Error Recovery Activity DECchip 21064 Load Lock Victim Processing The System-bus C_ERR L signal is asserted, the victim is written to memory coincident with the assertion of CUCERR L, and the read data is returned from the System-bus to the processor. The BCUE and BCUEA registers are frozen and the UNCORRECTABLE ERROR bit set. DECchip 21064 Store Conditional Victim Processing The System-bus C_ERR L signal is asserted, the victim is written to memory coincident with the assertion of CUCERR L, and the B-Cache is updated with the new data. The BCUE and BCUEA registers are frozen and the UNCORRECTABLE ERROR bit set. If store fails then no data cycles will occur; however C_ERR L will still be asserted. 8.3 Duplicate P-Cache Tag Store Parity Errors Duplicate P-Cache Tag Store Parity Errors can only be detected by the B-Cache controller when a System-bus write occurs. When an error is detected, the Cobra System-bus C_ERR L signal is asserted, and the B-Cache Duplicate Tag Store Error Register (DTSER) frozen, and the Error bit set. Detection of the parity error will force the invalidation of the associated Primary D-Cache location, and if HIT, the invalidation of the associated B-Cache location regardless of System-bus transaction commander ID. Thus single bit errors in the Duplicate Tag Store are not system fatal; however a HARDWARE ERROR INTERRUPT will occur every time one is encountered. 8.4 System-bus Errors System-bus errors may not be reportable as the error handling routines are most likely located in main memory. Only when the System-bus is still operable, and main memory has not been corrupted will System-bus errors be reportable. 8.4.1 C/A Parity Error When a System-bus node detects a C/A parity error, it will log the error, signal the system by asserting the C_ERR L signal and ignore the rest of the System-bus transaction. 186 Fault Management/Error Recovery
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Table 76: B-Cache Uncorrectable Errors<br />
Copyright © 1993 Digital Equipment Corporation.<br />
Transaction Causing<br />
Probe Access Reason Error Recovery Activity<br />
System-bus READ (Dirty)<br />
or Exchange (Read Dirty)<br />
System-bus READ / EX-<br />
CHANGE Dirty<br />
System-bus Write Probe If HIT System-bus write data<br />
has either bad parity or has<br />
CUCERR L<br />
Assert System-bus CUCERR L with the data<br />
returned to the System-bus.<br />
The B-Cache Uncorrectable Error (BCUE) and<br />
B-Cache Uncorrectable Error Address Registers<br />
(BCUEA) are frozen and the UNCOR-<br />
RECTABLE ERROR bit set.<br />
The B-Cache is written with BAD EDC.<br />
DECchip 21064 Read Block Victim Processing The System-bus C_ERR L signal is asserted,<br />
the victim written to memory coincident with<br />
the assertion of CUCERR L and the cycle is<br />
acknowledged to the processor with HARD_<br />
ERROR.<br />
The B-Cache is not updated, and B-Cache allocation<br />
is disabled.<br />
The BCUE and BCUEA registers are frozen<br />
and the UNCORRECTABLE ERROR bit set.<br />
System-bus returned data<br />
with bad System-bus parity<br />
or<br />
CUCERR L asserted with<br />
read data<br />
DECchip 21064 Write Block Victim Processing / Shared<br />
Masked Write<br />
The System-bus C_ERR L signal is asserted,<br />
bad "second" read data from the System-bus<br />
is returned to the processor, bad "second" data<br />
from the System-bus is written with "bad EDC"<br />
in the B-Cache,<br />
The BCUE and BCUEA registers are frozen<br />
and the UNCORRECTABLE ERROR bit set,<br />
processor is acknowledged with HARD_ERROR.<br />
The System-bus C_ERR L signal is asserted,<br />
the victim / shared write is written to memory<br />
coincident with the assertion of CUCERR L,<br />
and the B-Cache is updated with the new data.<br />
In the case of a shared masked write, the B-<br />
Cache longwords with failing EDC that are not<br />
updated by the processor write, will not be rewritten.<br />
The BCUE and BCUEA registers are frozen<br />
and the UNCORRECTABLE ERROR bit set.<br />
Fault Management/Error Recovery 185