Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Table 74: B-Cache Data Correctable Errors Copyright © 1993 Digital Equipment Corporation. Transaction Causing Probe Access Reason Error Recovery Activity System-bus READ (Dirty) or Exchange (Read Dirty) System-bus READ/ EXCHANGE Dirty System-bus Write — — The B-Cache Correctable Error (BCCE) and B-Cache Correctable Error Address Registers (BCCEA) are frozen and the CORRECTABLE ERROR bit set, if the BCC ENB B-CACHE COR ERR INTER- RUPT bit is set, the System-bus C_ERR L signal is asserted. DECchip 21064 Read Block Victim Processing The BCCE and BCCEA registers are frozen and the CORRECTABLE ERROR bit set if the BCC ENB B-CACHE COR ERR INTER- RUPT bit is set, the System-bus C_ERR L signal is asserted. DECchip 21064 Write Block Victim Processing / Shared Masked Write / Unmasked Write read allocate The BCCE and BCCEA registers are frozen and the CORRECTABLE ERROR bit set if the BCC ENB B-CACHE COR ERR INTER- RUPT bit is set, the System-bus C_ERR L signal is asserted. DECchip 21064 Load Lock Victim Processing The BCCE and BCCEA registers are frozen and the CORRECTABLE ERROR bit set, if the BCC ENB B-CACHE COR ERR INTER- RUPT bit is set, the System-bus C_ERR L signal is asserted. DECchip 21064 Store Conditional Victim Processing / Shared Masked Write The BCCE and BCCEA registers are frozen and the CORRECTABLE ERROR bit set if the BCC ENB B-CACHE COR ERR INTER- RUPT bit is set, the System-bus C_ERR L signal is asserted. 8.2.2.2 Uncorrectable Uncorrectable Data Store Errors can only be detected when either the B-Cache Controller or the 21064 processor read the B-Cache Data Store. Or when an EDC error occurs on the bus between the C³ chip and the 21064 processor. The mechanism used to report the error is different depending on which subsystem detected it. The severity of the error to the systems integrity depends on the address space the error occurred in as well as the state of the location in the B-Cache. Fault Management/Error Recovery 183
Copyright © 1993 Digital Equipment Corporation. Table 75: Uncorrectable Data Store Error Severity Matrix Address Context Dirty Severity User Yes Process Fatal if corrupted data used - Scrub No Scrub location - recoverable System Yes System Fatal if corrupted data used No Scrub location - recoverable The 21064 will detect Uncorrectable EDC errors only when executing a Load, or Load Lock instruction. When the error is detected the following sequence of events will occur: 1. Data put into I or D-Cache (appropriately) unchanged, block gets validated. 2. Machine check 3. BIU_STAT: FILL_EDC set, and FILL_IRD set for I-Stream reference cleared for D-Stream. (FILL_SEQ set if multiple errors occur.) 4. FILL_ADDR[33:5] & BIU_STAT[FILL_QW] gives bad quadword’s address 5. If D-Stream FILL_ADDR[4..2] contain PA bits [4..2] of location which the failing load instruction attempted to read. 6. FILL_SYNDROME contains syndrome bits associated with the failing quadword. 7. BIU_ADDR,BIU_STAT[6..0] locked - contents are UNPREDICTABLE 8. If I-Stream DC_STAT locked - contents are UNPREDICTABLE, If D-Stream DC_ STAT locked, RA identifies register which holds the bad data, LW,LOCK,INT,VAX_ FP identify type of load instruction 9. BC_TAG holds the results of the external cache tag probe if the external cache was enabled for this transaction. When detected by the 21064 (as part of the machine check handler), if the physical address of the location with the Uncorrectable error is not resident in the B-Cache then the error was a bus error and should be re-tried. The B-Cache controller could detect the error under several different circumstances, and the way it is handled depends on how it was discovered. Table 76 shows the complete error handling matrix for B-Cache Data Uncorrectable errors detected by the B-Cache controller. Uncorrectable errors are detected/reported when a Systembus Reads HIT Dirty Locations, a B-Cache entry is victimized, or a masked write to a shared location occurs. When detected by the B-Cache Controller, if the physical address of the location with the Uncorrectable error is not resident in the B-Cache then the error was a bus error and severity of the error is the same as if a DIRTY B-Cache location was found with an Uncorrectable Error - this location should be flushed to main memory where it will be written with BAD EDC. 184 Fault Management/Error Recovery
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
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4.7.2 System-bus Error Register - C
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Table 38: System-bus Error Register
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Table 38 (Cont.): System-bus Error
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4.7.3 System-bus Error Address Low
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4.8 Multiprocessor Configuration CS
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4.9 System Interrupt Clear Register
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4.10 Address Lock Register - CSR13
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4.11 Miss Address Register - CSR14
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Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 153 and 154: Copyright © 1993 Digital Equipment
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
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Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218: 11.3 CPU Module Max DC Power Requir
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Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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