Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
7.2.1.4 Hardware 1 - Local I/O
Hardware 1 Interrupts are generated as a result of ‘‘Local I/O’’ device interrupt requests.
They occur as a result of normal device operation, and when device errors
are detected. For a complete description of the unique device interrupt request characteristics,
refer to the component specifications for the device in question.
When a Local I/O Interrupt is posted, the PALcode entered will read the Local Interrupt
Register located on the I/O module. This register contains a bit field indicating
which local I/O device posted the interrupt. (Several device interrupts could be
pending.) PALcode dispatches to the appropriate interrupt service routine based on
a priority scheme resident in the PALcode environment.
Local I/O Interrupts only are restricted to being serviced by a dedicated processor
(identified as the Primary processor). The Primary processor designation can be
made at system power-up, or moved from one processor to the other over time. This
requires that at any time, the processor not designated the Primary must mask off
the Local I/O Interrupt request line bit 1 in the 21064 Processor HIER Internal
Processor Register.
7.2.1.5 Hardware 3 - Interprocessor
Hardware 3 Interrupts are requested when a CPU requires the attention of itself or
another CPU.
The Interprocessor Interrupt Request Register is used to post an interrupt request to
a specific processor. Note that, like software interrupts, no indication is given as to
whether there is already an interprocessor interrupt pending when one is requested.
Therefore, the interprocessor interrupt service routine must not assume there is a
one-to-one correspondence between interrupts requested and interrupts generated.
Refer to the ALPHA System Reference Manual for the proper usage and definition
of Interprocessor interrupts.
7.2.1.6 Hardware 4 - Interval Timer
The Interval Timer interrupt occurs at a regular interval which allows the processor
to effectively schedule processing time to each process requiring attention.
The interval timer interrupt will regularly interrupt the processor every 976.5625
microseconds. The PALcode that handles this interrupt must update its copy of the
absolute time, copy it to register R4, clear the interrupt in the local System Interrupt
Clear Register, and then pass control to the interval timer interrupt routine.
7.2.1.7 Hardware 5 - System Events
System Events such as power system status changes, halt requests from the Operator
Control Panel, or Node Halt, or an SGEC on the I/O module are signaled via the
Hardware 5 Interrupt.
Actual Power system status, and Operator Control Panel halt request status must be
requested from each subsystem which is accomplished over the System Serial Control
bus.
Exceptions and Interrupts 177