Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Cobra-bus Parity Error
Cobra-bus Parity Errors indicate that a node on the Cobra-bus has a bad driver or
receiver, or a problem exists in the physical interconnect. It is unlikely that this is
a correctable error so the handler should attempt to discover which node is bad, and
if possible disable it so it won’t interfere with normal bus operation.
If no Uncorrectable error can be detected, then retrying the operation causing the
error maybe help to isolate it.
Generally when an uncorrectable error of this type is detected it is system fatal.
A C/A Parity Error may result in the C/A not ack’ed bit being set in one of the
commander CSR’s. This is due to the fact that responders will not ack a C/A that
has bad parity. Refer to Section 7.1.1.3.10 for further details.
Invalid Cobra-bus Address Bystander
When and Invalid Cobra-bus Address is broadcast by a CPU node, and not ack’ed,
the Cobra-bus C_ERR L signal is asserted. The CPU that initiated the transaction
will machine check and receive a Hardware Error Interrupt; the bystander CPU will
only receive the Interrupt. The transaction initiator should handle the logging/error
recovery for this error. This results in an access violation. Refer to Section 7.1.1.3.11
for further details.
Invalid Cobra-bus Address I/O Commander
When and Invalid Cobra-bus Address is broadcast by the I/O node, and not ack’ed,
the Cobra-bus C_ERR L signal is asserted. Both CPU’s will receive a Hardware Error
Interrupt; and one should be designated to handle the logging/error recovery.
Information found in the IO error register will indicate whether this error occurred
as a result of mailbox operations or DMA assesses and the logging and recovery can
be handled differently for each.
Memory Uncorrectable EDC Error I/O Commander
When an Uncorrectable EDC Error is detected while the I/O module is the Cobrabus
Commander, the I/O module asserts the C_ERR L signal which causes the CPU
modules to receive a Hardware Error Interrupt. When this occurs, one CPU should
be designated to handle the logging/error recovery. This may or may not be SYSTEM
FATAL.
Memory Correctable EDC Error
When a Correctable EDC Error is detected the Memory module will assert the C_
ERR L signal if the Enable CRD reporting bit is set in Memory module CSR6. This
in turn causes the CPU module(s) to receive a Hardware Error Interrupt. When this
occurs, one CPU should be designated to handle the scrubbing/logging activity.
Duplicate Tag Store Parity Error
Duplicate tag store parity errors are treated in hardware as uncorrectable errors;
however the system will always recover from a parity error of this sort without any
loss of data and/or memory coherence.
176 Exceptions and Interrupts