Sable CPU Module Specification
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Sable CPU Module Specification

Sable CPU Module Specification Sable CPU Module Specification

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Copyright © 1993 Digital Equipment Corporation. 7.1.1.1 PAL Priority Level Below is the prioritized list of the exceptions that can occur on a Sable System. This list goes from the highest to the lowest priority. Table 69: Exception Priority/PAL Offset/SCB Offset/IPL Priority Description PAL Offset (h) SCB Offset (h) IPL (h) 1 HALT 0000 NA NA 2 Machine Check 0020 0660 31 3 0020 0670 31 4 DTB Miss -PAL 09E0 NA NA 5 DTB Miss -NATIVE 08E0 NA NA 6 ITB Miss 03E0 NA NA 7 ITB Access Violate 07E0 0080-00C0 X 8 Data Access Fault 01E0 0080-00C0 X 9 Unaligned Data 11E0 0300-03F0 X 10 Arithmetic -NFPU 17E0 0010 X 11 Arithmetic -ARTH 17E0 0200 X 12 Reserve Opcode Fault 13E0 0420 X 7.1.1.2 PALcode 0020 Entry Characteristics Exceptions occur as a direct† result of the detection of errors during the execution of the current instruction. The PALcode found at the PALentry 0020(h) must sift through the system error information and determine the severity of the error. In some cases the PALcode at this entry may correct the error and allow the machine to continue execution without any higher level software intervention. 7.1.1.3 PAL Routine Behavior 7.1.1.3.1 B-Cache Tag Parity Error † Except during ‘‘disconnected’’ write operations which occur as a result of masked write operations causing two consecutive Cobra-bus transactions. If an error is detected between the completion of the first Cobra-bus transaction, and the second (due to an unrelated intervening Cobra-bus transaction) a machine check will occur and the information relating to the actual error is logged in the C4-CSR’s. Software can determine when this occurs by comparing the address in the EV-EXC_ADDR register to the address locked in the C4-CSR’s. Exceptions and Interrupts 169

Copyright © 1993 Digital Equipment Corporation. Current CPU B-Cache Tag Parity Error Processor Detected Restricted to reads only, PAL must scrub the parity error from the Tag store using the standard B-Cache initialization procedure, and if the Dirty bit on the cache block in question is set, a SYSTEM FATAL Error should be signaled to the system software. Otherwise only error logging is required. Refer to Chapter 8, Section 8.2.1 for further details. 7.1.1.3.2 B-Cache Tag Control Parity Error Current CPU B-Cache Tag Control Parity Error Processor Detected Restricted to reads only, PAL must scrub the parity error from the Tag Control store using the standard B-Cache initialization procedure. This error is FATAL to the context the cached location is referenced in. Refer to Chapter 8, Section 8.2.1 for further details. 7.1.1.3.3 B-Cache Data Single Bit EDC Error Current CPU B-Cache EDC Error Processor Detected Restricted to reads only, PAL must scrub the EDC error from the Data store using the 21064 Processor B-Cache force Hit mode. Then the instruction that encountered the error should be restarted. A CRD interrupt should be dispatched. There is no way to determine if the failure was due to a B-Cache SRAM fault or a fault on the bus between the C4 and the 21064 processor chip. If the location found in the B-Cache does not have the same address as the address found in the EV-FILL_ADDR register then the error occurred on the data bus between the 21064 and C4. Generally this type of error is indicative of a hard fault; however if a simple test of the interface passes then the error may be recoverable after scrubbing affected locations and restarting the failing instruction. Refer to Chapter 8, Section 8.2.2 for further details. 7.1.1.3.4 B-Cache Data Uncorrectable EDC Error Current CPU B-Cache EDC Error Processor Detected Restricted to reads only, PAL must scrub the EDC error from the Data store using the 21064 B-Cache force Hit mode. If the Dirty bit on the cache block is set, the error is FATAL to the context the cached location is referenced in. Otherwise the error should be scrubbed from the cache and the failing instruction restarted. 170 Exceptions and Interrupts

Copyright © 1993 Digital Equipment Corporation.<br />

Current <strong>CPU</strong> B-Cache Tag Parity Error Processor Detected<br />

Restricted to reads only, PAL must scrub the parity error from the Tag store using the<br />

standard B-Cache initialization procedure, and if the Dirty bit on the cache block in<br />

question is set, a SYSTEM FATAL Error should be signaled to the system software.<br />

Otherwise only error logging is required.<br />

Refer to Chapter 8, Section 8.2.1 for further details.<br />

7.1.1.3.2 B-Cache Tag Control Parity Error<br />

Current <strong>CPU</strong> B-Cache Tag Control Parity Error Processor Detected<br />

Restricted to reads only, PAL must scrub the parity error from the Tag Control store<br />

using the standard B-Cache initialization procedure. This error is FATAL to the<br />

context the cached location is referenced in.<br />

Refer to Chapter 8, Section 8.2.1 for further details.<br />

7.1.1.3.3 B-Cache Data Single Bit EDC Error<br />

Current <strong>CPU</strong> B-Cache EDC Error Processor Detected<br />

Restricted to reads only, PAL must scrub the EDC error from the Data store using<br />

the 21064 Processor B-Cache force Hit mode. Then the instruction that encountered<br />

the error should be restarted. A CRD interrupt should be dispatched.<br />

There is no way to determine if the failure was due to a B-Cache SRAM fault or<br />

a fault on the bus between the C4 and the 21064 processor chip. If the location<br />

found in the B-Cache does not have the same address as the address found in the<br />

EV-FILL_ADDR register then the error occurred on the data bus between the 21064<br />

and C4. Generally this type of error is indicative of a hard fault; however if a simple<br />

test of the interface passes then the error may be recoverable after scrubbing affected<br />

locations and restarting the failing instruction.<br />

Refer to Chapter 8, Section 8.2.2 for further details.<br />

7.1.1.3.4 B-Cache Data Uncorrectable EDC Error<br />

Current <strong>CPU</strong> B-Cache EDC Error Processor Detected<br />

Restricted to reads only, PAL must scrub the EDC error from the Data store using<br />

the 21064 B-Cache force Hit mode. If the Dirty bit on the cache block is set, the<br />

error is FATAL to the context the cached location is referenced in. Otherwise the<br />

error should be scrubbed from the cache and the failing instruction restarted.<br />

170 Exceptions and Interrupts

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