Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Table 65 (Cont.): System-bus Initiated Transactions - Control Flow Cycle Probe Result Status Activity Read HIT Duplicate Tag Store, or Lock Address (if valid) Clean Assert System-bus SHARED 1 . Set SHARED bit in Tag Control Store if not already set. Clean Assert System-bus SHARED. Write HIT X‡ IF (location found in P-Cache or Commander ID is I/O module or in ARB) THEN Update B-Cache (Clean, shared = no change) and assert System-bus SHARED ELSE Invalidate B-Cache location (clean,not shared) 134 . IF (HIT address lock register) THEN clear address lock. or IF (I/O conditional update set) THEN IF (location found in P-Cache) THEN Update B-Cache (Clean, shared = no change) and assert System-bus SHARED ELSE Invalidate B-Cache location (clean, not shared) 134 . IF (HIT address lock register) THEN clear address lock. Exchange HIT Dirty Assert System-bus DIRTY and SHARED. Address Lock not changed. Provide Read data to System-bus 123 . Clean Assert System-bus SHARED 13 . Address Lock not changed. Read MISS NA† NOP 13 . IF (HIT Address Lock register) THEN assert System-bus SHARED. Write MISS NA NOP 134 IF (WRITE address hits the address lock) THEN clear address lock. Exchange MISS NA NOP 13 . IF (READ address HIT Address Lock register ) THEN assert Systembus SHARED. IF (EXCHANGE write address hits the address lock) THEN clear address lock. NUT X NOP 3 1 B-Cache Controller Checks Tag Store and Control Store Parity. 2 B-Cache Controller Checks Data EDC. 3 System-bus interface Controller Checks System-bus Parity. 4 System-bus interface Controller Checks Duplicate Tag Store Parity. †Not Applicable ‡don’t care CPU Module Transactions 163
Copyright © 1993 Digital Equipment Corporation. NOTE The B-Cache TAG probe during an exchange cycle is for the Read data ONLY. 164 CPU Module Transactions
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
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Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 135 and 136: Copyright © 1993 Digital Equipment
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
Page 177: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218: 11.3 CPU Module Max DC Power Requir
Page 221 and 222: Figure 68: module clocks Cobra - b
Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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