Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 65 (Cont.): System-bus Initiated Transactions - Control Flow
Cycle
Probe Result
Status Activity
Read HIT Duplicate
Tag Store,
or Lock Address
(if valid)
Clean Assert System-bus SHARED 1 .
Set SHARED bit in Tag Control Store if not already set.
Clean Assert System-bus SHARED.
Write HIT X‡ IF (location found in P-Cache or Commander ID is I/O module or in
ARB) THEN Update B-Cache (Clean, shared = no change) and assert
System-bus SHARED
ELSE Invalidate B-Cache location (clean,not shared) 134 .
IF (HIT address lock register) THEN clear address lock.
or
IF (I/O conditional update set) THEN
IF (location found in P-Cache) THEN Update B-Cache (Clean,
shared = no change) and assert System-bus SHARED
ELSE Invalidate B-Cache location (clean, not shared) 134 .
IF (HIT address lock register) THEN clear address lock.
Exchange HIT Dirty Assert System-bus DIRTY and SHARED. Address Lock not changed.
Provide Read data to System-bus 123 .
Clean Assert System-bus SHARED 13 . Address Lock not changed.
Read MISS NA† NOP 13 .
IF (HIT Address Lock register) THEN assert System-bus SHARED.
Write MISS NA NOP 134
IF (WRITE address hits the address lock) THEN clear address lock.
Exchange MISS NA NOP 13 .
IF (READ address HIT Address Lock register ) THEN assert Systembus
SHARED.
IF (EXCHANGE write address hits the address lock) THEN clear address
lock.
NUT X NOP 3
1 B-Cache Controller Checks Tag Store and Control Store Parity.
2 B-Cache Controller Checks Data EDC.
3 System-bus interface Controller Checks System-bus Parity.
4 System-bus interface Controller Checks Duplicate Tag Store Parity.
†Not Applicable
‡don’t care
CPU Module Transactions 163