Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 64 (Cont.): Processor Initiated Transactions - Control Flow
Datum/Cache
Cycle Status Size Activity
STORE COND.
I/O
X X
• Request System-bus
• If the CUCERR_L signal is asserted by the responder
module during the first cycle 4 of a System-bus
transaction when the 21064 is performing a Store
Conditional to non-cacheable address space, then
the write will not complete, and the Store conditional
failed indicators will be signaled to the processor.
• Relinquish System-bus
• ACK write (conditionally)
Processor initiated transactions to non-cacheable address space may be retried by the
sytem bus (CERR_L asserted during cycle 3). When this occurs, the C4 will initiate
a retry of the transaction (READ or WRITE) without DECchip 21064 intervention
required. Multiple retries are allowed and a transaction will either be retried, complete
succesfully, or not be acknowledge (error condition). Retry is NOT supported to
cacheable address space.
5.3.2 System-bus Initiated
The CPU module System-bus interface controller provides B-Cache control when the
the System-bus is active.
The behavior of the System-bus interface controller is determined by the System-bus
transaction, and the state of the B-Cache control bits. Table 65 illustrates the control
flows for these cycles. The activity column shows the activity that occurs after the
processor has relinquished its ownership of the B-Cache and the B-Cache TAG probe
results are available.
Table 65: System-bus Initiated Transactions - Control Flow
Cycle
Probe Result
Status Activity
Read HIT B-Cache Dirty Assert System-bus DIRTY and SHARED set SHARED bit in Tag Control
Store if not already set, cache block remains DIRTY.
Provide Data to System-bus 12
1 B-Cache Controller Checks Tag Store and Control Store Parity.
2 B-Cache Controller Checks Data EDC.
162 CPU Module Transactions