Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

Copyright © 1993 Digital Equipment Corporation. Table 64 (Cont.): Processor Initiated Transactions - Control Flow Datum/Cache Cycle Status Size Activity X 32 bytes LOAD LOCK X X STORE COND - Cacheable X X 2Processor Checks Data EDC. 3Processor Checks Tag Store and Control Store Parity. 4 B-Cache Controller Checks Tag Store and Control Store Parity. 5B-Cache Controller Checks Data EDC. 6System-bus interface Controller Checks System-bus Parity. • Request System-bus 34 • System-bus WRITE cycle 5 • Relinquish System-bus • ACK write • Request System-bus • Probe B-Cache 4 • Same as generic read except if reference to cacheable address space then lock bit set after arbitrating for the System-bus; otherwise no change to lock bit. 6 (Lock bit VALID = TRUE, Lock Address = access address) (IF (B-Cache hit) THEN change Systembus read to NUT.) 2 • Relinquish System-bus • ACK read • Request System-bus • Probe B-Cache 4 • Same as generic write to except fails IF (Lock bit VALID = FALSE). (IF (write failed due to lock bit not set) THEN change System-bus write to NUT.) • Relinquish System-bus • ACK write (conditionally) CPU Module Transactions 161
Copyright © 1993 Digital Equipment Corporation. Table 64 (Cont.): Processor Initiated Transactions - Control Flow Datum/Cache Cycle Status Size Activity STORE COND. I/O X X • Request System-bus • If the CUCERR_L signal is asserted by the responder module during the first cycle 4 of a System-bus transaction when the 21064 is performing a Store Conditional to non-cacheable address space, then the write will not complete, and the Store conditional failed indicators will be signaled to the processor. • Relinquish System-bus • ACK write (conditionally) Processor initiated transactions to non-cacheable address space may be retried by the sytem bus (CERR_L asserted during cycle 3). When this occurs, the C4 will initiate a retry of the transaction (READ or WRITE) without DECchip 21064 intervention required. Multiple retries are allowed and a transaction will either be retried, complete succesfully, or not be acknowledge (error condition). Retry is NOT supported to cacheable address space. 5.3.2 System-bus Initiated The CPU module System-bus interface controller provides B-Cache control when the the System-bus is active. The behavior of the System-bus interface controller is determined by the System-bus transaction, and the state of the B-Cache control bits. Table 65 illustrates the control flows for these cycles. The activity column shows the activity that occurs after the processor has relinquished its ownership of the B-Cache and the B-Cache TAG probe results are available. Table 65: System-bus Initiated Transactions - Control Flow Cycle Probe Result Status Activity Read HIT B-Cache Dirty Assert System-bus DIRTY and SHARED set SHARED bit in Tag Control Store if not already set, cache block remains DIRTY. Provide Data to System-bus 12 1 B-Cache Controller Checks Tag Store and Control Store Parity. 2 B-Cache Controller Checks Data EDC. 162 CPU Module Transactions
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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4.3.1 Duplicate Tag Error Register
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4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 135 and 136: Copyright © 1993 Digital Equipment
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
Page 175: Copyright © 1993 Digital Equipment
Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
Page 217 and 218: 11.3 CPU Module Max DC Power Requir
Page 221 and 222: Figure 68: module clocks Cobra - b
Page 223 and 224: Table 85 (Cont.): System bus AC and
Page 225 and 226: APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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