Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 64 (Cont.): Processor Initiated Transactions - Control Flow
Datum/Cache
Cycle Status Size Activity
Write MISS No Victim / Clean
Victim
< 32 bytes ‘‘Multiple-Arb Operation’’
Dirty Victim < 32 bytes ‘‘Multiple-Arb Operation’’
Enable Allocate
Disabled (BCC bit
0 clear)
1Refer to Section 4.2 for details.
3Processor Checks Tag Store and Control Store Parity.
4 B-Cache Controller Checks Tag Store and Control Store Parity.
5B-Cache Controller Checks Data EDC.
6System-bus interface Controller Checks System-bus Parity.
160 CPU Module Transactions
• Request System-bus 34
• System-bus READ cycle 6
• Cache block allocated (SHARED = System-bus
share during read, DIRTY = FALSE)
• Continue to request System-bus
• Write data merged with cache block (SHARED =
SHARED, DIRTY = FALSE)
• System-bus WRITE cycle 15
• Update B-Cache
• Relinquish System-bus
• ACK write
• Request System-bus 34
• System-bus EXCHANGE cycle 56
• Cache block allocated (SHARED = System-bus
share during read, DIRTY = FALSE)
• Continue to request System-bus
• Write data merged with cache block (SHARED =
SHARED, DIRTY = FALSE)
• System-bus WRITE cycle 15
• Update B-Cache
• Relinquish System-bus
• ACK write
< 32 bytes ‘‘Multiple-Arb Operation’’
• Request System-bus
• If B-Cache probe dirty then System-bus EXCHANGE
cycle 6
• If B-Cache probe not dirty then System-bus READ
cycle 6
• Update Cache block (VALID = NOT VALID)
• Continue to request System-bus
• System-bus WRITE cycle from merge buffer
• Relinquish System-bus
• ACK write