Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
5.3 Control Flow of CPU Module Transactions
5.3.1 Processor Initiated
The CPU module B-Cache controller provides B-Cache control under the following
circumstances. A B-Cache miss occurs, a LDxC, STxC, FETCH/FETCHM, or a MB
is executed, or when a write to a shared cache block is detected.
The behavior of the B-Cache controller is based on the current processor cycle type,
the state of the B-Cache control bits, and the state of the System-bus. The following
table illustrates the control flows for these cycles.
Table 64: Processor Initiated Transactions - Control Flow
Datum/Cache
Cycle Status Size Activity
Read HIT† X‡ X
Write HIT NOT Shared† X
Shared 32 bytes
1Refer to Section 4.2 for details.
2Processor Checks Data EDC.
3Processor Checks Tag Store and Control Store Parity.
4 B-Cache Controller Checks Tag Store and Control Store Parity.
5B-Cache Controller Checks Data EDC.
†‘‘Fast Cache’’ cycles, external logic does not intervene
‡X - don’t care
158 CPU Module Transactions
• Block read - Processor managed 32
• Update duplicate tag store
• Block written (DIRTY = TRUE) - Processor managed 3
• Request System-bus 345
• System-bus WRITE cycle 15
• Update Cache block (DIRTY = FALSE, SHARED =
System-bus shared during write)
• Relinquish System-bus
• ACK write