Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
As the System-bus is based on a ‘‘snooping’’ protocol, every System-bus transaction
is monitored by all System-bus participants. The memory modules can only act as
responders or bystanders, and as such only respond to requests from bus commanders.
The Processor and I/O subsystems can act as either commanders, responders,
or bystanders.
Table 63: System-bus Initiated Transactions
Transaction Abbrv
Systembus
cycles Activity
Write WR 6 B-Cache probe;
9 IF HIT update/invalidate
IF update pull System-bus SHARED, cache block
SHARED = prev SHARED
Read RD 7 B-Cache probe; Provide data if HIT dirty
Exchange XD 7 B-Cache probe (READ); Provide data if HIT dirty
No-op Transaction NUT 7 No operation
Refer to Table 65 for a detailed description of the control flows for System-bus initiated
cycles.
5.2.1 CPU as Commander
When one of the CPU module’s processors requests data that isn’t resident on the
CPU module, a request is passed to the System-bus interface controller, and a
System-bus transaction is initiated.
5.2.2 CPU as Bystander
The CPU module is a Bystander when some other System-bus commander has requested
data from a resource on the System-bus that doesn’t reside exclusively on
the CPU module.
As a Bystander, each B-Cache controller may have to update or invalidate a stale datum,
or provide dirty data to the System-bus thereby pre-empting a memory module
from returning stale data (for that transaction only).
5.2.3 CPU as Responder
The CPU module is a Responder when some other System-bus commander has requested
data from a System-bus visible CPU module register.
CPU Module Transactions 157