Sable CPU Module Specification

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$Suleiman Souhlal 904-344-811 Math 4175 Project 1 In this report ...$

5.1.2 Cacheable vs Non-Cacheable vs Allocate-Invalid Copyright © 1993 Digital Equipment Corporation. Cacheable Only ‘‘memory like’’ locations will be cached. These are defined as those locations with address bits 32 and 33 equal to ‘‘0’’. These locations will be placed in the B- Cache when it is enabled as a side effect of the processor issuing a READ_BLOCK. They will also be placed in the P-Cache as the read data will be acknowledged with OK. Non-Cacheable ‘‘Non-memory like’’ locations will not be cached. These are defined as those locations with address bits 32 or 33 equal to ‘‘1’’. These locations will not be placed in the B- Cache, and the read data will be acknowledged with OK_NCACHE. Writes to Non- Cacheable space are restricted to aligned quadword accesses only. The quadword write data is presented to the system-bus in the proper quadword associated with the address of the access. The data presented in the other quadwords of the cache block (during that system-bus cycle) is undefined; however the correct system-bus parity will be driven. No read merge will occur. All I/O locations are Non-Cacheable locations. Allocate-Invalid When the ENB B-CACHE INIT bit in the BCC register is clear, ‘‘Memory like’’ locations with address bit 33 equal to ‘‘0’’ and address bit 32 equal to ‘‘1’’, and address bit 31 equal to "0", will be treated as Cacheable locations to be allocated in the B- Cache as invalid. Read references to locations in this address space are intercepted by the C4 and cause either an EXCHANGE, or a READ request on the System-bus (depending on the state of the DIRTY bit of the cache block in question). Address bit 32 will be masked off before the address is presented on the System-bus to provide a legal Cobra System-bus address. When the read data is returned, the cache block in the B-Cache will be marked invalid. When the ENB B-CACHE INIT bit in the BCC register is set, ‘‘Memory like’’ locations with address bit 33 equal to ‘‘0’’ and address bit 32 equal to ‘‘1’’,and address bit 31 equal to "0", will be treated as Cacheable locations to be allocated in the B-Cache. Read references to locations in this address space are intercepted by C4 and cause the data found in the local CPU modules CSR8 (CBEAL) to be returned as the read data and subsequently filled into the B-Cache. Address bit 32 is passed through the C4 and presented to the System-bus. The C4 acknowledges the transaction itself, and the other CPU module will not probe its B-Cache. Refer to the definition of the B-Cache Control and Status Register, and Section 9.2 for further details. This feature can be used to just flush dirty entries from the cache, and/or to also guarentee that all cache entries are marked invalid. Simple flushing of dirty entries can be accomplished by setting the FORCE SHARED bit in the CBCTL register, and then walking the Allocate-Invalid address space to flush the cache (a process at low CPU Module Transactions 155
Copyright © 1993 Digital Equipment Corporation. IPL). When the full cache address space (nominally 1-4MB) has been accessed, the cache is guarenteed to be clean; however not necessarily invalid. If the routine that flushes the cache operates at an IPL higher than any other processes can execute, then when complete, the cache will be clean and marked completely invalid. NOTE As the bus interface re-maps all references through Allocate-Invalid space by clearing address bit 32 and presenting the resulting address to the memory subsystem. Only privledged processes should be allowed to map Allocate- Invalid space into their virtual address space. Figure 65: Address Space Map 0.0000.0000 0.8000.0000 1.0000.0000 1.8000.0000 2.0000.0000 Cacheable (2 GB) Reserved Cacheable (2 GB) (2 GB) Allocate-invalid (2 GB) non-cacheable Non-cacheable (8 GB) 5.2 System-bus Transactions CPU_MAP.DOC @ 50% There are four System-bus transaction types. These are READ, WRITE, EX- CHANGE, and NUT. READ, and WRITE transactions consist of a Command/Address cycle followed by two data cycles. The EXCHANGE transaction, which is used for dirty victim processing, consists of a Command/Address cycle followed by four data cycles, two write and two read. The NUT transaction consists of a Command/Address cycle only. Refer to the Cbus Version 2 specification for a more detailed description of the Systembus. 156 CPU Module Transactions
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Sable CPU Module Specification This
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CONTENTS Preface ..................
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3.9.6 Data Cache Address Register (
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7.1.1 Exception Handling ..........
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11.4 Environmental Specifications -
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25 MM_CSR .........................
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27 Base Addresses for CSRs . . . ..
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Preface Scope and Organization of t
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Copyright © 1993 Digital Equipment
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CHAPTER 1 CPU MODULE COMPONENTS AND
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1.2 The Alpha AXP Architecture Copy
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CHAPTER 4 FUNCTIONS LOCATED ELSEWHE
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Figure 41: B-Cache Control Register
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Table 28 (Cont.): B-Cache Control R
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Table 28 (Cont.): B-Cache Control R
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Page 119 and 120: Copyright © 1993 Digital Equipment
Page 121 and 122: 4.3.1 Duplicate Tag Error Register
Page 123 and 124: 4.5 Lack of Cache Block Prefetch Co
Page 125 and 126: Table 37: System-bus Control Regist
Page 127 and 128: 4.7.2 System-bus Error Register - C
Page 129 and 130: Table 38: System-bus Error Register
Page 131 and 132: Table 38 (Cont.): System-bus Error
Page 133 and 134: 4.7.3 System-bus Error Address Low
Page 137 and 138: 4.8 Multiprocessor Configuration CS
Page 139 and 140: 4.9 System Interrupt Clear Register
Page 141 and 142: 4.10 Address Lock Register - CSR13
Page 143 and 144: 4.11 Miss Address Register - CSR14
Page 145 and 146: Table 46 (Cont.): C4 Revision Regis
Page 147 and 148: Table 48 (Cont.): Interval Timer In
Page 149 and 150: Table 50: D-bus Microcontroller Clo
Page 151 and 152: Figure 58: Granting Order rule 4 CP
Page 155 and 156: Table 54 (Cont.): BIU_CTL Field Des
Page 157 and 158: Table 57: CPU EEPROM Defaults Locat
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Page 211 and 212: CHAPTER 11 PHYSICAL AND ELECTRICAL
Page 213 and 214: Table 81 (Cont.): MCA240 J5 SIDE 1
Page 215 and 216: Table 82 (Cont.): MCA44 J1 Side 1 S
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Figure 68: module clocks Cobra - b
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Table 85 (Cont.): System bus AC and
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APPENDIX A ALPHA ARCHITECTURE OPTIO
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INDEX 21064 IEEE floating point con
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Icache, 59 ICCSR, 19 IEEE Floating
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STQC cycle, 144 STxC cycle, 144 STx
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Sable CPU Module Specification

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