Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Serial Control Bus Based on the Signetics I²C; this bus is used on the Cobra System for intercommunication
of system components as well as error reporting. Refer to the Cobra System
Overview for further details.
Masked Write A write cycle that only updates a subset of nominal data block. (for example, A single
longword update to a cache block)
Memory Like
• Each page frame in the region either exists in its entirety or does not exist in its
entirety; there are no holes within a page frame.
• All locations are read/write.
• A write to a location followed by a read from that location returns precisely the
bits written; all bits act as memory.
• A write to one location does not change any other location.
• Reads have no side effects.
• Longword access granularity is provided.
• Instruction-fetch is supported.
• Load-locked and store-conditional are supported.
MISS Indicates that a copy of a desired memory location is not in a cache.
Non-memory Like Non-memory like regions may have arbitrary behavior. There may be un-implemented
locations or bits anywhere; some locations or bits may be read-only and others writeonly;
address ranges may overlap, such that a write to one location changes the bits
read from a different location; reads may have side effects; longword granularity need
not be supported; instruction-fetch need not be supported; and load-locked and storeconditional
need not be supported.
P-Cache The Primary Cache memory subsystem inside the 21064 processor including its control
machines. The Primary Cache is the cache that is the fastest and closest to the
processor.
PROBE The act of using the current operation address (Cobra-bus or processor) to perform a
cache line lookup to determine if the line is valid and/or must be invalidated, updated,
or returned.
PROCESS FATAL An error that is only fatal to the process(es) whose context the error occurred in.
ERROR
Read-Merge The term Read-Merge indicates that an item is read from a responder/bystander, and
new data is then added to the returned read data. This occurs when a masked write
cycle is requested by the processor, or when unmasked cycles occur and the CPU is
configured to allocate on full block write misses.
RESPONDER A Cobra-bus node which accepts or supplies data in response to an address and
command from a Cobra-bus commander.
SHARED With reference to a cache block in the cache of a Cobra-bus node, the cache block is
valid and it is valid in at least one other cache of another Cobra-bus node.
SNOOP For a cached node, the act of monitoring Cobra-bus transactions to determine whether
the node has a copy of a cache line.
Snooping Protocol A cache coherence protocol whereby all nodes on a common system bus monitor all
bus activity. This allows a node to keep it’s copy of a particular datum up to date,
and/or supply data to the bus when it has the newest copy. Refer to the Cobra System
Bus Specification and Chapter 5 for further details.
SYSTEM FATAL ER-
ROR
An error that is fatal to system as the error occurred in the context of a system process,
or if the context of an error can not be determined.
TRANSACTION A sequence of cycles which comprise a complete bus operation.
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