Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
5.1.1.7 BARRIER TRANSACTION
The BARRIER transaction appears on the external interface as a result of an MB
instruction. The acknowledgment of the BARRIER transaction tells the 21064 that
all invalidates have been supplied to it, and that any external write buffers have
been pushed out to the coherence point. Any errors detected during these operations
can be reported to the 21064 when the BARRIER transaction is acknowledged. The
Cobra CPU will immediately acknowledge this transaction because it does not buffer
block_write transactions.
Figure 63: BARRIER TRANSACTION
Cycle
sysClkOut1_h
cReq_h
cAck_h
0 1 2
LJ-01871-TI0
1. The BARRIER transaction begins. The 21064 places the command code for BAR-
RIER onto the cReq_h outputs.
2. The external logic notices the BARRIER command, and because it has completed
processing the command (it isn’t going to do anything), it places an acknowledge
code on the cAck_h inputs.
3. The 21064 detects the acknowledge on cAck_h, and removes the command. The
external logic removes the acknowledge code from cAck_h. The cycle is finished.
5.1.1.8 FETCH TRANSACTION
A FETCH transaction appears on the external interface as a result of a FETCH
instruction. The transaction supplies an address to the external logic, which the
system chooses to ignore and responds with an immediate acknowledge.
CPU Module Transactions 153