Sable CPU Module Specification

Figure 62: WRITE BLOCK
Cycle
sysClkOut1_h
adr_h
RAM Ctl
data_h
check_h
cReq_h
cWMask_h
dOE_l
dWSel_h
cAck_h
0 1 2 3 4 5
Copyright © 1993 Digital Equipment Corporation.
6
LJ-01868-TI0
1. The cReq_h pins are always idle in the system clock cycle immediately before
the beginning of an external transaction. The adr_h pins always change to their
final value (with respect to a particular external transaction) at least one CPU
cycle before the start of the transaction.
2. The WRITE_BLOCK cycle begins. The 21064 has already placed the address of
the block on adr_h. The 21064 places the longword valid masks on cWMask_h
and a WRITE_BLOCK command code on cReq_h. The 21064 will clear dataA_
h[4..3] and tagCEOE_h no later than one CPU cycle after the system clock edge
at which the transaction begins. The 21064 clears dataCEOE_h[3..0] at least one
CPU cycle before the system clock edge at which the transaction begins.
3. The external logic detects the command, and asserts dOE_l to tell the 21064 to
drive the first 16 bytes of the block onto the data bus.
4. The 21064 drives the first 16 bytes of write data onto the data_h and check_h
busses, and the external logic writes it into the destination. Although a single
stall cycle has been shown here, there could be no stall cycles, or many stall
cycles.
CPU Module Transactions 151