Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
5. The external logic obtains the second 16 bytes of data. Although a single stall
cycle has been shown here, there could be no stall cycles, or many stall cycles.
6. The external logic has the second 16 bytes of data. It places it on the data_h and
check_h busses. It asserts dRAck_h to tell the 21064 that the data and check bit
busses are valid. The 21064 detects dRAck_h at the end of this cycle, and reads
in the second 16 bytes of data at the same time. In addition, the external logic
places an acknowledge code on cAck_h to tell the 21064 that the READ_BLOCK
cycle is completed. The 21064 detects the acknowledge at the end of this cycle,
and may change the address.
7. Everything is idle. The 21064 could start a new external cache cycle at this time.
Because external logic owns the RAMs by virtue of the 21064 having deasserted its
RAM control signals at the beginning of the transaction, external logic may cache
the data by asserting its write pulses on the external cache during cycles 3 and 5.
The 21064 performs EDC checking on the data supplied to it via the data and check
busses if so requested by the acknowledge code. It is not necessary to place data into
the external cache to get checking.
5.1.1.4 WRITE_BLOCK
A WRITE_BLOCK transaction appears at the external interface on external cache
write misses (either because it really was a miss, or because the external cache has
not been enabled), or on external cache write hits to shared blocks.
150 CPU Module Transactions