Sable CPU Module Specification

Copyright © 1993 Digital Equipment Corporation.
Table 62: Processor Initiated Transactions
TRANSACTION Activity
P-Cache Read Not Visible outside Processor
P-Cache Write B-Cache Written if Hit
Write Block Generated if Miss
P-Cache Masked Write B-Cache Written if Hit
Write Block Generated if Miss
Fast B-Cache Read Hit B-Cache data read
Fast B-Cache Write Hit Data written to B-Cache data store, Dirty bit set
Fast B-Cache Masked Write Hit Data written to B-Cache data store, Dirty bit set
Read Block 1
System-bus read or exchange cycle generated
Write Block 2
System-bus read or exchange and possibly write or nut cycles generated
LDxL - Load Lock System-bus read, exchange, or nut cycle generated,
IF (cacheable address space reference) THEN address latched and
Lock bit set
IF (Non-cacheable address space) THEN no change to address lock
or lock bit.
STxC - Store Conditional System-bus read, exchange and possibly nut or write cycles generated,
IF (cacheable address space reference) Lock bit cleared (it was set)
store completes
Barrier 3
FETCH/FETCHM 4
1Generated as a result of a Fast B-Cache Read Miss.
2Generated as a result of a Fast B-Cache Write Miss.
3Generated as a result of the execution of a Memory Barrier Instruction.
4 Generated as a result of the execution of a FETCH or FETCHM Instruction.
5.1.1 21064 Processor TRANSACTIONS
IF (Non-cacheable address space) THEN no change to lock bit, store
failed if responder asserts UC_ERR L during cycle.
All data buffers flushed to system coherence point. Acknowledge
request, no other module level activity.
Acknowledge Request, no other module level activity.
5.1.1.1 FAST EXTERNAL CACHE READ HIT
A fast external cache read consists of a probe read (overlapped with the first data
read), followed by the second data read if the probe hits. The following diagram
illustrates the Cobra CPU fast external cache read which selects 4 CPU cycle reads
(BC_RD_SPD = 3), 4 CPU cycle writes (BC_WR_SPD = 3), chip enable control OE =
L).
146 CPU Module Transactions